diff options
author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
---|---|---|
committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:30 +0300 |
commit | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (patch) | |
tree | 012bb94d777798f1f56ac1cec429509766d05181 /contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h | |
parent | 6751af0b0c1b952fede40b19b71da8025b5d8bcf (diff) | |
download | ydb-2598ef1d0aee359b4b6d5fdd1758916d5907d04f.tar.gz |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 1 of 2.
Diffstat (limited to 'contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h')
-rw-r--r-- | contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h b/contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h index b4e39214c9..bd0ff64222 100644 --- a/contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h +++ b/contrib/libs/llvm12/include/llvm/CodeGen/VirtRegMap.h @@ -26,7 +26,7 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/TargetRegisterInfo.h" -#include "llvm/CodeGen/TileShapeInfo.h" +#include "llvm/CodeGen/TileShapeInfo.h" #include "llvm/Pass.h" #include <cassert> @@ -68,10 +68,10 @@ class TargetInstrInfo; /// mapping. IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap; - /// Virt2ShapeMap - For X86 AMX register whose register is bound shape - /// information. - DenseMap<unsigned, ShapeT> Virt2ShapeMap; - + /// Virt2ShapeMap - For X86 AMX register whose register is bound shape + /// information. + DenseMap<unsigned, ShapeT> Virt2ShapeMap; + /// createSpillSlot - Allocate a spill slot for RC from MFI. unsigned createSpillSlot(const TargetRegisterClass *RC); @@ -110,30 +110,30 @@ class TargetInstrInfo; /// returns the physical register mapped to the specified /// virtual register - MCRegister getPhys(Register virtReg) const { + MCRegister getPhys(Register virtReg) const { assert(virtReg.isVirtual()); - return MCRegister::from(Virt2PhysMap[virtReg.id()]); + return MCRegister::from(Virt2PhysMap[virtReg.id()]); } /// creates a mapping for the specified virtual register to /// the specified physical register void assignVirt2Phys(Register virtReg, MCPhysReg physReg); - bool isShapeMapEmpty() const { return Virt2ShapeMap.empty(); } - - bool hasShape(Register virtReg) const { - return getShape(virtReg).isValid(); - } - - ShapeT getShape(Register virtReg) const { - assert(virtReg.isVirtual()); - return Virt2ShapeMap.lookup(virtReg); - } - - void assignVirt2Shape(Register virtReg, ShapeT shape) { - Virt2ShapeMap[virtReg.id()] = shape; - } - + bool isShapeMapEmpty() const { return Virt2ShapeMap.empty(); } + + bool hasShape(Register virtReg) const { + return getShape(virtReg).isValid(); + } + + ShapeT getShape(Register virtReg) const { + assert(virtReg.isVirtual()); + return Virt2ShapeMap.lookup(virtReg); + } + + void assignVirt2Shape(Register virtReg, ShapeT shape) { + Virt2ShapeMap[virtReg.id()] = shape; + } + /// clears the specified virtual register's, physical /// register mapping void clearVirt(Register virtReg) { @@ -158,15 +158,15 @@ class TargetInstrInfo; bool hasKnownPreference(Register VirtReg); /// records virtReg is a split live interval from SReg. - void setIsSplitFromReg(Register virtReg, Register SReg) { + void setIsSplitFromReg(Register virtReg, Register SReg) { Virt2SplitMap[virtReg.id()] = SReg; - if (hasShape(SReg)) { - Virt2ShapeMap[virtReg.id()] = getShape(SReg); - } + if (hasShape(SReg)) { + Virt2ShapeMap[virtReg.id()] = getShape(SReg); + } } /// returns the live interval virtReg is split from. - Register getPreSplitReg(Register virtReg) const { + Register getPreSplitReg(Register virtReg) const { return Virt2SplitMap[virtReg.id()]; } @@ -174,8 +174,8 @@ class TargetInstrInfo; /// from through splitting. /// A register that was not created by splitting is its own original. /// This operation is idempotent. - Register getOriginal(Register VirtReg) const { - Register Orig = getPreSplitReg(VirtReg); + Register getOriginal(Register VirtReg) const { + Register Orig = getPreSplitReg(VirtReg); return Orig ? Orig : VirtReg; } |