diff options
| author | shadchin <shadchin@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
|---|---|---|
| committer | Daniil Cherednik <dcherednik@yandex-team.ru> | 2022-02-10 16:44:39 +0300 |
| commit | e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0 (patch) | |
| tree | 64175d5cadab313b3e7039ebaa06c5bc3295e274 /contrib/libs/libunwind | |
| parent | 2598ef1d0aee359b4b6d5fdd1758916d5907d04f (diff) | |
| download | ydb-e9656aae26e0358d5378e5b63dcac5c8dbe0e4d0.tar.gz | |
Restoring authorship annotation for <shadchin@yandex-team.ru>. Commit 2 of 2.
Diffstat (limited to 'contrib/libs/libunwind')
| -rw-r--r-- | contrib/libs/libunwind/include/__libunwind_config.h | 44 | ||||
| -rw-r--r-- | contrib/libs/libunwind/include/libunwind.h | 304 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/DwarfInstructions.hpp | 2 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/Registers.hpp | 1044 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/Unwind-sjlj.c | 24 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/UnwindCursor.hpp | 208 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/UnwindRegistersRestore.S | 384 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/UnwindRegistersSave.S | 420 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/assembly.h | 98 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/config.h | 12 | ||||
| -rw-r--r-- | contrib/libs/libunwind/src/libunwind.cpp | 6 |
11 files changed, 1273 insertions, 1273 deletions
diff --git a/contrib/libs/libunwind/include/__libunwind_config.h b/contrib/libs/libunwind/include/__libunwind_config.h index d907fdf0e9..e87bcf4003 100644 --- a/contrib/libs/libunwind/include/__libunwind_config.h +++ b/contrib/libs/libunwind/include/__libunwind_config.h @@ -26,12 +26,12 @@ #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC64 31 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64 -#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE 143 +#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE 143 #if defined(_LIBUNWIND_IS_NATIVE_ONLY) -# if defined(__linux__) -# define _LIBUNWIND_TARGET_LINUX 1 -# endif +# if defined(__linux__) +# define _LIBUNWIND_TARGET_LINUX 1 +# endif # if defined(__i386__) # define _LIBUNWIND_TARGET_I386 # define _LIBUNWIND_CONTEXT_SIZE 8 @@ -138,26 +138,26 @@ #define _LIBUNWIND_CONTEXT_SIZE 16 #define _LIBUNWIND_CURSOR_SIZE 23 # elif defined(__riscv) -# define _LIBUNWIND_TARGET_RISCV 1 -# if defined(__riscv_flen) -# define RISCV_FLEN __riscv_flen +# define _LIBUNWIND_TARGET_RISCV 1 +# if defined(__riscv_flen) +# define RISCV_FLEN __riscv_flen +# else +# define RISCV_FLEN 0 +# endif +# define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64) +# if __riscv_xlen == 32 +# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7) +# elif __riscv_xlen == 64 +# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12) # else -# define RISCV_FLEN 0 +# error "Unsupported RISC-V ABI" # endif -# define _LIBUNWIND_CONTEXT_SIZE (32 * (__riscv_xlen + RISCV_FLEN) / 64) -# if __riscv_xlen == 32 -# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 7) -# elif __riscv_xlen == 64 -# define _LIBUNWIND_CURSOR_SIZE (_LIBUNWIND_CONTEXT_SIZE + 12) -# else -# error "Unsupported RISC-V ABI" -# endif # define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV -# elif defined(__ve__) -# define _LIBUNWIND_TARGET_VE 1 -# define _LIBUNWIND_CONTEXT_SIZE 67 -# define _LIBUNWIND_CURSOR_SIZE 79 -# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE +# elif defined(__ve__) +# define _LIBUNWIND_TARGET_VE 1 +# define _LIBUNWIND_CONTEXT_SIZE 67 +# define _LIBUNWIND_CURSOR_SIZE 79 +# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE # else # error "Unsupported architecture." # endif @@ -175,7 +175,7 @@ # define _LIBUNWIND_TARGET_SPARC64 1 # define _LIBUNWIND_TARGET_HEXAGON 1 # define _LIBUNWIND_TARGET_RISCV 1 -# define _LIBUNWIND_TARGET_VE 1 +# define _LIBUNWIND_TARGET_VE 1 # define _LIBUNWIND_CONTEXT_SIZE 167 # define _LIBUNWIND_CURSOR_SIZE 179 # define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287 diff --git a/contrib/libs/libunwind/include/libunwind.h b/contrib/libs/libunwind/include/libunwind.h index 1166e0ffbb..8303c1a04c 100644 --- a/contrib/libs/libunwind/include/libunwind.h +++ b/contrib/libs/libunwind/include/libunwind.h @@ -1022,156 +1022,156 @@ enum { UNW_RISCV_F31 = 63, }; -// VE register numbers -enum { - UNW_VE_S0 = 0, - UNW_VE_S1 = 1, - UNW_VE_S2 = 2, - UNW_VE_S3 = 3, - UNW_VE_S4 = 4, - UNW_VE_S5 = 5, - UNW_VE_S6 = 6, - UNW_VE_S7 = 7, - UNW_VE_S8 = 8, - UNW_VE_S9 = 9, - UNW_VE_S10 = 10, - UNW_VE_S11 = 11, - UNW_VE_S12 = 12, - UNW_VE_S13 = 13, - UNW_VE_S14 = 14, - UNW_VE_S15 = 15, - UNW_VE_S16 = 16, - UNW_VE_S17 = 17, - UNW_VE_S18 = 18, - UNW_VE_S19 = 19, - UNW_VE_S20 = 20, - UNW_VE_S21 = 21, - UNW_VE_S22 = 22, - UNW_VE_S23 = 23, - UNW_VE_S24 = 24, - UNW_VE_S25 = 25, - UNW_VE_S26 = 26, - UNW_VE_S27 = 27, - UNW_VE_S28 = 28, - UNW_VE_S29 = 29, - UNW_VE_S30 = 30, - UNW_VE_S31 = 31, - UNW_VE_S32 = 32, - UNW_VE_S33 = 33, - UNW_VE_S34 = 34, - UNW_VE_S35 = 35, - UNW_VE_S36 = 36, - UNW_VE_S37 = 37, - UNW_VE_S38 = 38, - UNW_VE_S39 = 39, - UNW_VE_S40 = 40, - UNW_VE_S41 = 41, - UNW_VE_S42 = 42, - UNW_VE_S43 = 43, - UNW_VE_S44 = 44, - UNW_VE_S45 = 45, - UNW_VE_S46 = 46, - UNW_VE_S47 = 47, - UNW_VE_S48 = 48, - UNW_VE_S49 = 49, - UNW_VE_S50 = 50, - UNW_VE_S51 = 51, - UNW_VE_S52 = 52, - UNW_VE_S53 = 53, - UNW_VE_S54 = 54, - UNW_VE_S55 = 55, - UNW_VE_S56 = 56, - UNW_VE_S57 = 57, - UNW_VE_S58 = 58, - UNW_VE_S59 = 59, - UNW_VE_S60 = 60, - UNW_VE_S61 = 61, - UNW_VE_S62 = 62, - UNW_VE_S63 = 63, - UNW_VE_V0 = 64 + 0, - UNW_VE_V1 = 64 + 1, - UNW_VE_V2 = 64 + 2, - UNW_VE_V3 = 64 + 3, - UNW_VE_V4 = 64 + 4, - UNW_VE_V5 = 64 + 5, - UNW_VE_V6 = 64 + 6, - UNW_VE_V7 = 64 + 7, - UNW_VE_V8 = 64 + 8, - UNW_VE_V9 = 64 + 9, - UNW_VE_V10 = 64 + 10, - UNW_VE_V11 = 64 + 11, - UNW_VE_V12 = 64 + 12, - UNW_VE_V13 = 64 + 13, - UNW_VE_V14 = 64 + 14, - UNW_VE_V15 = 64 + 15, - UNW_VE_V16 = 64 + 16, - UNW_VE_V17 = 64 + 17, - UNW_VE_V18 = 64 + 18, - UNW_VE_V19 = 64 + 19, - UNW_VE_V20 = 64 + 20, - UNW_VE_V21 = 64 + 21, - UNW_VE_V22 = 64 + 22, - UNW_VE_V23 = 64 + 23, - UNW_VE_V24 = 64 + 24, - UNW_VE_V25 = 64 + 25, - UNW_VE_V26 = 64 + 26, - UNW_VE_V27 = 64 + 27, - UNW_VE_V28 = 64 + 28, - UNW_VE_V29 = 64 + 29, - UNW_VE_V30 = 64 + 30, - UNW_VE_V31 = 64 + 31, - UNW_VE_V32 = 64 + 32, - UNW_VE_V33 = 64 + 33, - UNW_VE_V34 = 64 + 34, - UNW_VE_V35 = 64 + 35, - UNW_VE_V36 = 64 + 36, - UNW_VE_V37 = 64 + 37, - UNW_VE_V38 = 64 + 38, - UNW_VE_V39 = 64 + 39, - UNW_VE_V40 = 64 + 40, - UNW_VE_V41 = 64 + 41, - UNW_VE_V42 = 64 + 42, - UNW_VE_V43 = 64 + 43, - UNW_VE_V44 = 64 + 44, - UNW_VE_V45 = 64 + 45, - UNW_VE_V46 = 64 + 46, - UNW_VE_V47 = 64 + 47, - UNW_VE_V48 = 64 + 48, - UNW_VE_V49 = 64 + 49, - UNW_VE_V50 = 64 + 50, - UNW_VE_V51 = 64 + 51, - UNW_VE_V52 = 64 + 52, - UNW_VE_V53 = 64 + 53, - UNW_VE_V54 = 64 + 54, - UNW_VE_V55 = 64 + 55, - UNW_VE_V56 = 64 + 56, - UNW_VE_V57 = 64 + 57, - UNW_VE_V58 = 64 + 58, - UNW_VE_V59 = 64 + 59, - UNW_VE_V60 = 64 + 60, - UNW_VE_V61 = 64 + 61, - UNW_VE_V62 = 64 + 62, - UNW_VE_V63 = 64 + 63, - UNW_VE_VM0 = 128 + 0, - UNW_VE_VM1 = 128 + 1, - UNW_VE_VM2 = 128 + 2, - UNW_VE_VM3 = 128 + 3, - UNW_VE_VM4 = 128 + 4, - UNW_VE_VM5 = 128 + 5, - UNW_VE_VM6 = 128 + 6, - UNW_VE_VM7 = 128 + 7, - UNW_VE_VM8 = 128 + 8, - UNW_VE_VM9 = 128 + 9, - UNW_VE_VM10 = 128 + 10, - UNW_VE_VM11 = 128 + 11, - UNW_VE_VM12 = 128 + 12, - UNW_VE_VM13 = 128 + 13, - UNW_VE_VM14 = 128 + 14, - UNW_VE_VM15 = 128 + 15, // = 143 - - // Following registers don't have DWARF register numbers. - UNW_VE_VIXR = 144, - UNW_VE_VL = 145, -}; - +// VE register numbers +enum { + UNW_VE_S0 = 0, + UNW_VE_S1 = 1, + UNW_VE_S2 = 2, + UNW_VE_S3 = 3, + UNW_VE_S4 = 4, + UNW_VE_S5 = 5, + UNW_VE_S6 = 6, + UNW_VE_S7 = 7, + UNW_VE_S8 = 8, + UNW_VE_S9 = 9, + UNW_VE_S10 = 10, + UNW_VE_S11 = 11, + UNW_VE_S12 = 12, + UNW_VE_S13 = 13, + UNW_VE_S14 = 14, + UNW_VE_S15 = 15, + UNW_VE_S16 = 16, + UNW_VE_S17 = 17, + UNW_VE_S18 = 18, + UNW_VE_S19 = 19, + UNW_VE_S20 = 20, + UNW_VE_S21 = 21, + UNW_VE_S22 = 22, + UNW_VE_S23 = 23, + UNW_VE_S24 = 24, + UNW_VE_S25 = 25, + UNW_VE_S26 = 26, + UNW_VE_S27 = 27, + UNW_VE_S28 = 28, + UNW_VE_S29 = 29, + UNW_VE_S30 = 30, + UNW_VE_S31 = 31, + UNW_VE_S32 = 32, + UNW_VE_S33 = 33, + UNW_VE_S34 = 34, + UNW_VE_S35 = 35, + UNW_VE_S36 = 36, + UNW_VE_S37 = 37, + UNW_VE_S38 = 38, + UNW_VE_S39 = 39, + UNW_VE_S40 = 40, + UNW_VE_S41 = 41, + UNW_VE_S42 = 42, + UNW_VE_S43 = 43, + UNW_VE_S44 = 44, + UNW_VE_S45 = 45, + UNW_VE_S46 = 46, + UNW_VE_S47 = 47, + UNW_VE_S48 = 48, + UNW_VE_S49 = 49, + UNW_VE_S50 = 50, + UNW_VE_S51 = 51, + UNW_VE_S52 = 52, + UNW_VE_S53 = 53, + UNW_VE_S54 = 54, + UNW_VE_S55 = 55, + UNW_VE_S56 = 56, + UNW_VE_S57 = 57, + UNW_VE_S58 = 58, + UNW_VE_S59 = 59, + UNW_VE_S60 = 60, + UNW_VE_S61 = 61, + UNW_VE_S62 = 62, + UNW_VE_S63 = 63, + UNW_VE_V0 = 64 + 0, + UNW_VE_V1 = 64 + 1, + UNW_VE_V2 = 64 + 2, + UNW_VE_V3 = 64 + 3, + UNW_VE_V4 = 64 + 4, + UNW_VE_V5 = 64 + 5, + UNW_VE_V6 = 64 + 6, + UNW_VE_V7 = 64 + 7, + UNW_VE_V8 = 64 + 8, + UNW_VE_V9 = 64 + 9, + UNW_VE_V10 = 64 + 10, + UNW_VE_V11 = 64 + 11, + UNW_VE_V12 = 64 + 12, + UNW_VE_V13 = 64 + 13, + UNW_VE_V14 = 64 + 14, + UNW_VE_V15 = 64 + 15, + UNW_VE_V16 = 64 + 16, + UNW_VE_V17 = 64 + 17, + UNW_VE_V18 = 64 + 18, + UNW_VE_V19 = 64 + 19, + UNW_VE_V20 = 64 + 20, + UNW_VE_V21 = 64 + 21, + UNW_VE_V22 = 64 + 22, + UNW_VE_V23 = 64 + 23, + UNW_VE_V24 = 64 + 24, + UNW_VE_V25 = 64 + 25, + UNW_VE_V26 = 64 + 26, + UNW_VE_V27 = 64 + 27, + UNW_VE_V28 = 64 + 28, + UNW_VE_V29 = 64 + 29, + UNW_VE_V30 = 64 + 30, + UNW_VE_V31 = 64 + 31, + UNW_VE_V32 = 64 + 32, + UNW_VE_V33 = 64 + 33, + UNW_VE_V34 = 64 + 34, + UNW_VE_V35 = 64 + 35, + UNW_VE_V36 = 64 + 36, + UNW_VE_V37 = 64 + 37, + UNW_VE_V38 = 64 + 38, + UNW_VE_V39 = 64 + 39, + UNW_VE_V40 = 64 + 40, + UNW_VE_V41 = 64 + 41, + UNW_VE_V42 = 64 + 42, + UNW_VE_V43 = 64 + 43, + UNW_VE_V44 = 64 + 44, + UNW_VE_V45 = 64 + 45, + UNW_VE_V46 = 64 + 46, + UNW_VE_V47 = 64 + 47, + UNW_VE_V48 = 64 + 48, + UNW_VE_V49 = 64 + 49, + UNW_VE_V50 = 64 + 50, + UNW_VE_V51 = 64 + 51, + UNW_VE_V52 = 64 + 52, + UNW_VE_V53 = 64 + 53, + UNW_VE_V54 = 64 + 54, + UNW_VE_V55 = 64 + 55, + UNW_VE_V56 = 64 + 56, + UNW_VE_V57 = 64 + 57, + UNW_VE_V58 = 64 + 58, + UNW_VE_V59 = 64 + 59, + UNW_VE_V60 = 64 + 60, + UNW_VE_V61 = 64 + 61, + UNW_VE_V62 = 64 + 62, + UNW_VE_V63 = 64 + 63, + UNW_VE_VM0 = 128 + 0, + UNW_VE_VM1 = 128 + 1, + UNW_VE_VM2 = 128 + 2, + UNW_VE_VM3 = 128 + 3, + UNW_VE_VM4 = 128 + 4, + UNW_VE_VM5 = 128 + 5, + UNW_VE_VM6 = 128 + 6, + UNW_VE_VM7 = 128 + 7, + UNW_VE_VM8 = 128 + 8, + UNW_VE_VM9 = 128 + 9, + UNW_VE_VM10 = 128 + 10, + UNW_VE_VM11 = 128 + 11, + UNW_VE_VM12 = 128 + 12, + UNW_VE_VM13 = 128 + 13, + UNW_VE_VM14 = 128 + 14, + UNW_VE_VM15 = 128 + 15, // = 143 + + // Following registers don't have DWARF register numbers. + UNW_VE_VIXR = 144, + UNW_VE_VL = 145, +}; + #endif diff --git a/contrib/libs/libunwind/src/DwarfInstructions.hpp b/contrib/libs/libunwind/src/DwarfInstructions.hpp index 98c8fb2b40..c1a241c55c 100644 --- a/contrib/libs/libunwind/src/DwarfInstructions.hpp +++ b/contrib/libs/libunwind/src/DwarfInstructions.hpp @@ -236,7 +236,7 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc, // to a NOP on pre-v8.3a architectures. if ((R::getArch() == REGISTERS_ARM64) && prolog.savedRegisters[UNW_AARCH64_RA_SIGN_STATE].value && - returnAddress != 0) { + returnAddress != 0) { #if !defined(_LIBUNWIND_IS_NATIVE_ONLY) return UNW_ECROSSRASIGNING; #else diff --git a/contrib/libs/libunwind/src/Registers.hpp b/contrib/libs/libunwind/src/Registers.hpp index 7ab71ded44..cbc3876d67 100644 --- a/contrib/libs/libunwind/src/Registers.hpp +++ b/contrib/libs/libunwind/src/Registers.hpp @@ -38,7 +38,7 @@ enum { REGISTERS_SPARC64, REGISTERS_HEXAGON, REGISTERS_RISCV, - REGISTERS_VE, + REGISTERS_VE, }; #if defined(_LIBUNWIND_TARGET_I386) @@ -1868,7 +1868,7 @@ inline bool Registers_arm64::validRegister(int regNum) const { return false; if (regNum == UNW_AARCH64_RA_SIGN_STATE) return true; - if ((regNum > 32) && (regNum < 64)) + if ((regNum > 32) && (regNum < 64)) return false; return true; } @@ -1881,10 +1881,10 @@ inline uint64_t Registers_arm64::getRegister(int regNum) const { if (regNum == UNW_AARCH64_RA_SIGN_STATE) return _registers.__ra_sign_state; if (regNum == UNW_AARCH64_FP) - return _registers.__fp; + return _registers.__fp; if (regNum == UNW_AARCH64_LR) - return _registers.__lr; - if ((regNum >= 0) && (regNum < 29)) + return _registers.__lr; + if ((regNum >= 0) && (regNum < 29)) return _registers.__x[regNum]; _LIBUNWIND_ABORT("unsupported arm64 register"); } @@ -1897,10 +1897,10 @@ inline void Registers_arm64::setRegister(int regNum, uint64_t value) { else if (regNum == UNW_AARCH64_RA_SIGN_STATE) _registers.__ra_sign_state = value; else if (regNum == UNW_AARCH64_FP) - _registers.__fp = value; + _registers.__fp = value; else if (regNum == UNW_AARCH64_LR) - _registers.__lr = value; - else if ((regNum >= 0) && (regNum < 29)) + _registers.__lr = value; + else if ((regNum >= 0) && (regNum < 29)) _registers.__x[regNum] = value; else _LIBUNWIND_ABORT("unsupported arm64 register"); @@ -1977,7 +1977,7 @@ inline const char *Registers_arm64::getRegisterName(int regNum) { case UNW_AARCH64_SP: return "sp"; case UNW_AARCH64_PC: - return "pc"; + return "pc"; case UNW_AARCH64_V0: return "d0"; case UNW_AARCH64_V1: @@ -3954,51 +3954,51 @@ inline const char *Registers_hexagon::getRegisterName(int regNum) { #if defined(_LIBUNWIND_TARGET_RISCV) -/// Registers_riscv holds the register state of a thread in a RISC-V +/// Registers_riscv holds the register state of a thread in a RISC-V /// process. - -// This check makes it safe when LIBUNWIND_ENABLE_CROSS_UNWINDING enabled. -# ifdef __riscv -# if __riscv_xlen == 32 -typedef uint32_t reg_t; -# elif __riscv_xlen == 64 -typedef uint64_t reg_t; -# else -# error "Unsupported __riscv_xlen" -# endif - -# if defined(__riscv_flen) -# if __riscv_flen == 64 -typedef double fp_t; -# elif __riscv_flen == 32 -typedef float fp_t; -# else -# error "Unsupported __riscv_flen" -# endif -# else -// This is just for supressing undeclared error of fp_t. -typedef double fp_t; -# endif -# else -// Use Max possible width when cross unwinding -typedef uint64_t reg_t; -typedef double fp_t; -# define __riscv_xlen 64 -# define __riscv_flen 64 -#endif - -/// Registers_riscv holds the register state of a thread. + +// This check makes it safe when LIBUNWIND_ENABLE_CROSS_UNWINDING enabled. +# ifdef __riscv +# if __riscv_xlen == 32 +typedef uint32_t reg_t; +# elif __riscv_xlen == 64 +typedef uint64_t reg_t; +# else +# error "Unsupported __riscv_xlen" +# endif + +# if defined(__riscv_flen) +# if __riscv_flen == 64 +typedef double fp_t; +# elif __riscv_flen == 32 +typedef float fp_t; +# else +# error "Unsupported __riscv_flen" +# endif +# else +// This is just for supressing undeclared error of fp_t. +typedef double fp_t; +# endif +# else +// Use Max possible width when cross unwinding +typedef uint64_t reg_t; +typedef double fp_t; +# define __riscv_xlen 64 +# define __riscv_flen 64 +#endif + +/// Registers_riscv holds the register state of a thread. class _LIBUNWIND_HIDDEN Registers_riscv { public: Registers_riscv(); Registers_riscv(const void *registers); bool validRegister(int num) const; - reg_t getRegister(int num) const; - void setRegister(int num, reg_t value); + reg_t getRegister(int num) const; + void setRegister(int num, reg_t value); bool validFloatRegister(int num) const; - fp_t getFloatRegister(int num) const; - void setFloatRegister(int num, fp_t value); + fp_t getFloatRegister(int num) const; + void setFloatRegister(int num, fp_t value); bool validVectorRegister(int num) const; v128 getVectorRegister(int num) const; void setVectorRegister(int num, v128 value); @@ -4007,45 +4007,45 @@ public: static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV; } static int getArch() { return REGISTERS_RISCV; } - reg_t getSP() const { return _registers[2]; } - void setSP(reg_t value) { _registers[2] = value; } - reg_t getIP() const { return _registers[0]; } - void setIP(reg_t value) { _registers[0] = value; } + reg_t getSP() const { return _registers[2]; } + void setSP(reg_t value) { _registers[2] = value; } + reg_t getIP() const { return _registers[0]; } + void setIP(reg_t value) { _registers[0] = value; } private: // _registers[0] holds the pc - reg_t _registers[32]; -# if defined(__riscv_flen) - fp_t _floats[32]; -# endif + reg_t _registers[32]; +# if defined(__riscv_flen) + fp_t _floats[32]; +# endif }; inline Registers_riscv::Registers_riscv(const void *registers) { static_assert((check_fit<Registers_riscv, unw_context_t>::does_fit), "riscv registers do not fit into unw_context_t"); memcpy(&_registers, registers, sizeof(_registers)); -# if __riscv_xlen == 32 - static_assert(sizeof(_registers) == 0x80, - "expected float registers to be at offset 128"); -# elif __riscv_xlen == 64 +# if __riscv_xlen == 32 + static_assert(sizeof(_registers) == 0x80, + "expected float registers to be at offset 128"); +# elif __riscv_xlen == 64 static_assert(sizeof(_registers) == 0x100, "expected float registers to be at offset 256"); -# else -# error "Unexpected float registers." -# endif - -# if defined(__riscv_flen) +# else +# error "Unexpected float registers." +# endif + +# if defined(__riscv_flen) memcpy(_floats, static_cast<const uint8_t *>(registers) + sizeof(_registers), sizeof(_floats)); -# endif +# endif } inline Registers_riscv::Registers_riscv() { memset(&_registers, 0, sizeof(_registers)); -# if defined(__riscv_flen) +# if defined(__riscv_flen) memset(&_floats, 0, sizeof(_floats)); -# endif +# endif } inline bool Registers_riscv::validRegister(int regNum) const { @@ -4060,7 +4060,7 @@ inline bool Registers_riscv::validRegister(int regNum) const { return true; } -inline reg_t Registers_riscv::getRegister(int regNum) const { +inline reg_t Registers_riscv::getRegister(int regNum) const { if (regNum == UNW_REG_IP) return _registers[0]; if (regNum == UNW_REG_SP) @@ -4072,7 +4072,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const { _LIBUNWIND_ABORT("unsupported riscv register"); } -inline void Registers_riscv::setRegister(int regNum, reg_t value) { +inline void Registers_riscv::setRegister(int regNum, reg_t value) { if (regNum == UNW_REG_IP) _registers[0] = value; else if (regNum == UNW_REG_SP) @@ -4226,37 +4226,37 @@ inline const char *Registers_riscv::getRegisterName(int regNum) { } inline bool Registers_riscv::validFloatRegister(int regNum) const { -# if defined(__riscv_flen) +# if defined(__riscv_flen) if (regNum < UNW_RISCV_F0) return false; if (regNum > UNW_RISCV_F31) return false; return true; -# else - (void)regNum; - return false; -# endif +# else + (void)regNum; + return false; +# endif } -inline fp_t Registers_riscv::getFloatRegister(int regNum) const { -# if defined(__riscv_flen) +inline fp_t Registers_riscv::getFloatRegister(int regNum) const { +# if defined(__riscv_flen) assert(validFloatRegister(regNum)); return _floats[regNum - UNW_RISCV_F0]; -# else +# else (void)regNum; _LIBUNWIND_ABORT("libunwind not built with float support"); -# endif +# endif } -inline void Registers_riscv::setFloatRegister(int regNum, fp_t value) { -# if defined(__riscv_flen) +inline void Registers_riscv::setFloatRegister(int regNum, fp_t value) { +# if defined(__riscv_flen) assert(validFloatRegister(regNum)); _floats[regNum - UNW_RISCV_F0] = value; -# else +# else (void)regNum; (void)value; _LIBUNWIND_ABORT("libunwind not built with float support"); -# endif +# endif } inline bool Registers_riscv::validVectorRegister(int) const { @@ -4271,447 +4271,447 @@ inline void Registers_riscv::setVectorRegister(int, v128) { _LIBUNWIND_ABORT("no riscv vector register support yet"); } #endif // _LIBUNWIND_TARGET_RISCV - -#if defined(_LIBUNWIND_TARGET_VE) -/// Registers_ve holds the register state of a thread in a VE process. -class _LIBUNWIND_HIDDEN Registers_ve { -public: - Registers_ve(); - Registers_ve(const void *registers); - - bool validRegister(int num) const; - uint64_t getRegister(int num) const; - void setRegister(int num, uint64_t value); - bool validFloatRegister(int num) const; - double getFloatRegister(int num) const; - void setFloatRegister(int num, double value); - bool validVectorRegister(int num) const; - v128 getVectorRegister(int num) const; - void setVectorRegister(int num, v128 value); - static const char *getRegisterName(int num); - void jumpto(); - static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE; } - static int getArch() { return REGISTERS_VE; } - - uint64_t getSP() const { return _registers.__s[11]; } - void setSP(uint64_t value) { _registers.__s[11] = value; } - uint64_t getIP() const { return _registers.__ic; } - void setIP(uint64_t value) { _registers.__ic = value; } - -private: - // FIXME: Need to store not only scalar registers but also vector and vector - // mask registers. VEOS uses mcontext_t defined in ucontext.h. It takes - // 524288 bytes (65536*8 bytes), though. Currently, we use libunwind for - // SjLj exception support only, so Registers_ve is not implemented completely. - struct ve_thread_state_t { - uint64_t __s[64]; // s0-s64 - uint64_t __ic; // Instruction counter (IC) - uint64_t __vixr; // Vector Index Register - uint64_t __vl; // Vector Length Register - }; - - ve_thread_state_t _registers; // total 67 registers - - // Currently no vector register is preserved. -}; - -inline Registers_ve::Registers_ve(const void *registers) { - static_assert((check_fit<Registers_ve, unw_context_t>::does_fit), - "ve registers do not fit into unw_context_t"); - memcpy(&_registers, static_cast<const uint8_t *>(registers), - sizeof(_registers)); - static_assert(sizeof(_registers) == 536, - "expected vector register offset to be 536"); -} - -inline Registers_ve::Registers_ve() { - memset(&_registers, 0, sizeof(_registers)); -} - -inline bool Registers_ve::validRegister(int regNum) const { - if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) - return true; - - switch (regNum) { - case UNW_REG_IP: - case UNW_REG_SP: - case UNW_VE_VIXR: - case UNW_VE_VL: - return true; - default: - return false; - } -} - -inline uint64_t Registers_ve::getRegister(int regNum) const { - if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) - return _registers.__s[regNum - UNW_VE_S0]; - - switch (regNum) { - case UNW_REG_IP: - return _registers.__ic; - case UNW_REG_SP: - return _registers.__s[11]; - case UNW_VE_VIXR: - return _registers.__vixr; - case UNW_VE_VL: - return _registers.__vl; - } - _LIBUNWIND_ABORT("unsupported ve register"); -} - -inline void Registers_ve::setRegister(int regNum, uint64_t value) { - if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) { - _registers.__s[regNum - UNW_VE_S0] = value; - return; - } - - switch (regNum) { - case UNW_REG_IP: - _registers.__ic = value; - return; - case UNW_REG_SP: - _registers.__s[11] = value; - return; - case UNW_VE_VIXR: - _registers.__vixr = value; - return; - case UNW_VE_VL: - _registers.__vl = value; - return; - } - _LIBUNWIND_ABORT("unsupported ve register"); -} - -inline bool Registers_ve::validFloatRegister(int /* regNum */) const { - return false; -} - -inline double Registers_ve::getFloatRegister(int /* regNum */) const { - _LIBUNWIND_ABORT("VE doesn't have float registers"); -} - -inline void Registers_ve::setFloatRegister(int /* regNum */, - double /* value */) { - _LIBUNWIND_ABORT("VE doesn't have float registers"); -} - -inline bool Registers_ve::validVectorRegister(int /* regNum */) const { - return false; -} - -inline v128 Registers_ve::getVectorRegister(int /* regNum */) const { - _LIBUNWIND_ABORT("VE vector support not implemented"); -} - -inline void Registers_ve::setVectorRegister(int /* regNum */, - v128 /* value */) { - _LIBUNWIND_ABORT("VE vector support not implemented"); -} - -inline const char *Registers_ve::getRegisterName(int regNum) { - switch (regNum) { - case UNW_REG_IP: - return "ip"; - case UNW_REG_SP: - return "sp"; - case UNW_VE_VIXR: - return "vixr"; - case UNW_VE_VL: - return "vl"; - case UNW_VE_S0: - return "s0"; - case UNW_VE_S1: - return "s1"; - case UNW_VE_S2: - return "s2"; - case UNW_VE_S3: - return "s3"; - case UNW_VE_S4: - return "s4"; - case UNW_VE_S5: - return "s5"; - case UNW_VE_S6: - return "s6"; - case UNW_VE_S7: - return "s7"; - case UNW_VE_S8: - return "s8"; - case UNW_VE_S9: - return "s9"; - case UNW_VE_S10: - return "s10"; - case UNW_VE_S11: - return "s11"; - case UNW_VE_S12: - return "s12"; - case UNW_VE_S13: - return "s13"; - case UNW_VE_S14: - return "s14"; - case UNW_VE_S15: - return "s15"; - case UNW_VE_S16: - return "s16"; - case UNW_VE_S17: - return "s17"; - case UNW_VE_S18: - return "s18"; - case UNW_VE_S19: - return "s19"; - case UNW_VE_S20: - return "s20"; - case UNW_VE_S21: - return "s21"; - case UNW_VE_S22: - return "s22"; - case UNW_VE_S23: - return "s23"; - case UNW_VE_S24: - return "s24"; - case UNW_VE_S25: - return "s25"; - case UNW_VE_S26: - return "s26"; - case UNW_VE_S27: - return "s27"; - case UNW_VE_S28: - return "s28"; - case UNW_VE_S29: - return "s29"; - case UNW_VE_S30: - return "s30"; - case UNW_VE_S31: - return "s31"; - case UNW_VE_S32: - return "s32"; - case UNW_VE_S33: - return "s33"; - case UNW_VE_S34: - return "s34"; - case UNW_VE_S35: - return "s35"; - case UNW_VE_S36: - return "s36"; - case UNW_VE_S37: - return "s37"; - case UNW_VE_S38: - return "s38"; - case UNW_VE_S39: - return "s39"; - case UNW_VE_S40: - return "s40"; - case UNW_VE_S41: - return "s41"; - case UNW_VE_S42: - return "s42"; - case UNW_VE_S43: - return "s43"; - case UNW_VE_S44: - return "s44"; - case UNW_VE_S45: - return "s45"; - case UNW_VE_S46: - return "s46"; - case UNW_VE_S47: - return "s47"; - case UNW_VE_S48: - return "s48"; - case UNW_VE_S49: - return "s49"; - case UNW_VE_S50: - return "s50"; - case UNW_VE_S51: - return "s51"; - case UNW_VE_S52: - return "s52"; - case UNW_VE_S53: - return "s53"; - case UNW_VE_S54: - return "s54"; - case UNW_VE_S55: - return "s55"; - case UNW_VE_S56: - return "s56"; - case UNW_VE_S57: - return "s57"; - case UNW_VE_S58: - return "s58"; - case UNW_VE_S59: - return "s59"; - case UNW_VE_S60: - return "s60"; - case UNW_VE_S61: - return "s61"; - case UNW_VE_S62: - return "s62"; - case UNW_VE_S63: - return "s63"; - case UNW_VE_V0: - return "v0"; - case UNW_VE_V1: - return "v1"; - case UNW_VE_V2: - return "v2"; - case UNW_VE_V3: - return "v3"; - case UNW_VE_V4: - return "v4"; - case UNW_VE_V5: - return "v5"; - case UNW_VE_V6: - return "v6"; - case UNW_VE_V7: - return "v7"; - case UNW_VE_V8: - return "v8"; - case UNW_VE_V9: - return "v9"; - case UNW_VE_V10: - return "v10"; - case UNW_VE_V11: - return "v11"; - case UNW_VE_V12: - return "v12"; - case UNW_VE_V13: - return "v13"; - case UNW_VE_V14: - return "v14"; - case UNW_VE_V15: - return "v15"; - case UNW_VE_V16: - return "v16"; - case UNW_VE_V17: - return "v17"; - case UNW_VE_V18: - return "v18"; - case UNW_VE_V19: - return "v19"; - case UNW_VE_V20: - return "v20"; - case UNW_VE_V21: - return "v21"; - case UNW_VE_V22: - return "v22"; - case UNW_VE_V23: - return "v23"; - case UNW_VE_V24: - return "v24"; - case UNW_VE_V25: - return "v25"; - case UNW_VE_V26: - return "v26"; - case UNW_VE_V27: - return "v27"; - case UNW_VE_V28: - return "v28"; - case UNW_VE_V29: - return "v29"; - case UNW_VE_V30: - return "v30"; - case UNW_VE_V31: - return "v31"; - case UNW_VE_V32: - return "v32"; - case UNW_VE_V33: - return "v33"; - case UNW_VE_V34: - return "v34"; - case UNW_VE_V35: - return "v35"; - case UNW_VE_V36: - return "v36"; - case UNW_VE_V37: - return "v37"; - case UNW_VE_V38: - return "v38"; - case UNW_VE_V39: - return "v39"; - case UNW_VE_V40: - return "v40"; - case UNW_VE_V41: - return "v41"; - case UNW_VE_V42: - return "v42"; - case UNW_VE_V43: - return "v43"; - case UNW_VE_V44: - return "v44"; - case UNW_VE_V45: - return "v45"; - case UNW_VE_V46: - return "v46"; - case UNW_VE_V47: - return "v47"; - case UNW_VE_V48: - return "v48"; - case UNW_VE_V49: - return "v49"; - case UNW_VE_V50: - return "v50"; - case UNW_VE_V51: - return "v51"; - case UNW_VE_V52: - return "v52"; - case UNW_VE_V53: - return "v53"; - case UNW_VE_V54: - return "v54"; - case UNW_VE_V55: - return "v55"; - case UNW_VE_V56: - return "v56"; - case UNW_VE_V57: - return "v57"; - case UNW_VE_V58: - return "v58"; - case UNW_VE_V59: - return "v59"; - case UNW_VE_V60: - return "v60"; - case UNW_VE_V61: - return "v61"; - case UNW_VE_V62: - return "v62"; - case UNW_VE_V63: - return "v63"; - case UNW_VE_VM0: - return "vm0"; - case UNW_VE_VM1: - return "vm1"; - case UNW_VE_VM2: - return "vm2"; - case UNW_VE_VM3: - return "vm3"; - case UNW_VE_VM4: - return "vm4"; - case UNW_VE_VM5: - return "vm5"; - case UNW_VE_VM6: - return "vm6"; - case UNW_VE_VM7: - return "vm7"; - case UNW_VE_VM8: - return "vm8"; - case UNW_VE_VM9: - return "vm9"; - case UNW_VE_VM10: - return "vm10"; - case UNW_VE_VM11: - return "vm11"; - case UNW_VE_VM12: - return "vm12"; - case UNW_VE_VM13: - return "vm13"; - case UNW_VE_VM14: - return "vm14"; - case UNW_VE_VM15: - return "vm15"; - } - return "unknown register"; -} -#endif // _LIBUNWIND_TARGET_VE - + +#if defined(_LIBUNWIND_TARGET_VE) +/// Registers_ve holds the register state of a thread in a VE process. +class _LIBUNWIND_HIDDEN Registers_ve { +public: + Registers_ve(); + Registers_ve(const void *registers); + + bool validRegister(int num) const; + uint64_t getRegister(int num) const; + void setRegister(int num, uint64_t value); + bool validFloatRegister(int num) const; + double getFloatRegister(int num) const; + void setFloatRegister(int num, double value); + bool validVectorRegister(int num) const; + v128 getVectorRegister(int num) const; + void setVectorRegister(int num, v128 value); + static const char *getRegisterName(int num); + void jumpto(); + static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_VE; } + static int getArch() { return REGISTERS_VE; } + + uint64_t getSP() const { return _registers.__s[11]; } + void setSP(uint64_t value) { _registers.__s[11] = value; } + uint64_t getIP() const { return _registers.__ic; } + void setIP(uint64_t value) { _registers.__ic = value; } + +private: + // FIXME: Need to store not only scalar registers but also vector and vector + // mask registers. VEOS uses mcontext_t defined in ucontext.h. It takes + // 524288 bytes (65536*8 bytes), though. Currently, we use libunwind for + // SjLj exception support only, so Registers_ve is not implemented completely. + struct ve_thread_state_t { + uint64_t __s[64]; // s0-s64 + uint64_t __ic; // Instruction counter (IC) + uint64_t __vixr; // Vector Index Register + uint64_t __vl; // Vector Length Register + }; + + ve_thread_state_t _registers; // total 67 registers + + // Currently no vector register is preserved. +}; + +inline Registers_ve::Registers_ve(const void *registers) { + static_assert((check_fit<Registers_ve, unw_context_t>::does_fit), + "ve registers do not fit into unw_context_t"); + memcpy(&_registers, static_cast<const uint8_t *>(registers), + sizeof(_registers)); + static_assert(sizeof(_registers) == 536, + "expected vector register offset to be 536"); +} + +inline Registers_ve::Registers_ve() { + memset(&_registers, 0, sizeof(_registers)); +} + +inline bool Registers_ve::validRegister(int regNum) const { + if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) + return true; + + switch (regNum) { + case UNW_REG_IP: + case UNW_REG_SP: + case UNW_VE_VIXR: + case UNW_VE_VL: + return true; + default: + return false; + } +} + +inline uint64_t Registers_ve::getRegister(int regNum) const { + if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) + return _registers.__s[regNum - UNW_VE_S0]; + + switch (regNum) { + case UNW_REG_IP: + return _registers.__ic; + case UNW_REG_SP: + return _registers.__s[11]; + case UNW_VE_VIXR: + return _registers.__vixr; + case UNW_VE_VL: + return _registers.__vl; + } + _LIBUNWIND_ABORT("unsupported ve register"); +} + +inline void Registers_ve::setRegister(int regNum, uint64_t value) { + if (regNum >= UNW_VE_S0 && regNum <= UNW_VE_S63) { + _registers.__s[regNum - UNW_VE_S0] = value; + return; + } + + switch (regNum) { + case UNW_REG_IP: + _registers.__ic = value; + return; + case UNW_REG_SP: + _registers.__s[11] = value; + return; + case UNW_VE_VIXR: + _registers.__vixr = value; + return; + case UNW_VE_VL: + _registers.__vl = value; + return; + } + _LIBUNWIND_ABORT("unsupported ve register"); +} + +inline bool Registers_ve::validFloatRegister(int /* regNum */) const { + return false; +} + +inline double Registers_ve::getFloatRegister(int /* regNum */) const { + _LIBUNWIND_ABORT("VE doesn't have float registers"); +} + +inline void Registers_ve::setFloatRegister(int /* regNum */, + double /* value */) { + _LIBUNWIND_ABORT("VE doesn't have float registers"); +} + +inline bool Registers_ve::validVectorRegister(int /* regNum */) const { + return false; +} + +inline v128 Registers_ve::getVectorRegister(int /* regNum */) const { + _LIBUNWIND_ABORT("VE vector support not implemented"); +} + +inline void Registers_ve::setVectorRegister(int /* regNum */, + v128 /* value */) { + _LIBUNWIND_ABORT("VE vector support not implemented"); +} + +inline const char *Registers_ve::getRegisterName(int regNum) { + switch (regNum) { + case UNW_REG_IP: + return "ip"; + case UNW_REG_SP: + return "sp"; + case UNW_VE_VIXR: + return "vixr"; + case UNW_VE_VL: + return "vl"; + case UNW_VE_S0: + return "s0"; + case UNW_VE_S1: + return "s1"; + case UNW_VE_S2: + return "s2"; + case UNW_VE_S3: + return "s3"; + case UNW_VE_S4: + return "s4"; + case UNW_VE_S5: + return "s5"; + case UNW_VE_S6: + return "s6"; + case UNW_VE_S7: + return "s7"; + case UNW_VE_S8: + return "s8"; + case UNW_VE_S9: + return "s9"; + case UNW_VE_S10: + return "s10"; + case UNW_VE_S11: + return "s11"; + case UNW_VE_S12: + return "s12"; + case UNW_VE_S13: + return "s13"; + case UNW_VE_S14: + return "s14"; + case UNW_VE_S15: + return "s15"; + case UNW_VE_S16: + return "s16"; + case UNW_VE_S17: + return "s17"; + case UNW_VE_S18: + return "s18"; + case UNW_VE_S19: + return "s19"; + case UNW_VE_S20: + return "s20"; + case UNW_VE_S21: + return "s21"; + case UNW_VE_S22: + return "s22"; + case UNW_VE_S23: + return "s23"; + case UNW_VE_S24: + return "s24"; + case UNW_VE_S25: + return "s25"; + case UNW_VE_S26: + return "s26"; + case UNW_VE_S27: + return "s27"; + case UNW_VE_S28: + return "s28"; + case UNW_VE_S29: + return "s29"; + case UNW_VE_S30: + return "s30"; + case UNW_VE_S31: + return "s31"; + case UNW_VE_S32: + return "s32"; + case UNW_VE_S33: + return "s33"; + case UNW_VE_S34: + return "s34"; + case UNW_VE_S35: + return "s35"; + case UNW_VE_S36: + return "s36"; + case UNW_VE_S37: + return "s37"; + case UNW_VE_S38: + return "s38"; + case UNW_VE_S39: + return "s39"; + case UNW_VE_S40: + return "s40"; + case UNW_VE_S41: + return "s41"; + case UNW_VE_S42: + return "s42"; + case UNW_VE_S43: + return "s43"; + case UNW_VE_S44: + return "s44"; + case UNW_VE_S45: + return "s45"; + case UNW_VE_S46: + return "s46"; + case UNW_VE_S47: + return "s47"; + case UNW_VE_S48: + return "s48"; + case UNW_VE_S49: + return "s49"; + case UNW_VE_S50: + return "s50"; + case UNW_VE_S51: + return "s51"; + case UNW_VE_S52: + return "s52"; + case UNW_VE_S53: + return "s53"; + case UNW_VE_S54: + return "s54"; + case UNW_VE_S55: + return "s55"; + case UNW_VE_S56: + return "s56"; + case UNW_VE_S57: + return "s57"; + case UNW_VE_S58: + return "s58"; + case UNW_VE_S59: + return "s59"; + case UNW_VE_S60: + return "s60"; + case UNW_VE_S61: + return "s61"; + case UNW_VE_S62: + return "s62"; + case UNW_VE_S63: + return "s63"; + case UNW_VE_V0: + return "v0"; + case UNW_VE_V1: + return "v1"; + case UNW_VE_V2: + return "v2"; + case UNW_VE_V3: + return "v3"; + case UNW_VE_V4: + return "v4"; + case UNW_VE_V5: + return "v5"; + case UNW_VE_V6: + return "v6"; + case UNW_VE_V7: + return "v7"; + case UNW_VE_V8: + return "v8"; + case UNW_VE_V9: + return "v9"; + case UNW_VE_V10: + return "v10"; + case UNW_VE_V11: + return "v11"; + case UNW_VE_V12: + return "v12"; + case UNW_VE_V13: + return "v13"; + case UNW_VE_V14: + return "v14"; + case UNW_VE_V15: + return "v15"; + case UNW_VE_V16: + return "v16"; + case UNW_VE_V17: + return "v17"; + case UNW_VE_V18: + return "v18"; + case UNW_VE_V19: + return "v19"; + case UNW_VE_V20: + return "v20"; + case UNW_VE_V21: + return "v21"; + case UNW_VE_V22: + return "v22"; + case UNW_VE_V23: + return "v23"; + case UNW_VE_V24: + return "v24"; + case UNW_VE_V25: + return "v25"; + case UNW_VE_V26: + return "v26"; + case UNW_VE_V27: + return "v27"; + case UNW_VE_V28: + return "v28"; + case UNW_VE_V29: + return "v29"; + case UNW_VE_V30: + return "v30"; + case UNW_VE_V31: + return "v31"; + case UNW_VE_V32: + return "v32"; + case UNW_VE_V33: + return "v33"; + case UNW_VE_V34: + return "v34"; + case UNW_VE_V35: + return "v35"; + case UNW_VE_V36: + return "v36"; + case UNW_VE_V37: + return "v37"; + case UNW_VE_V38: + return "v38"; + case UNW_VE_V39: + return "v39"; + case UNW_VE_V40: + return "v40"; + case UNW_VE_V41: + return "v41"; + case UNW_VE_V42: + return "v42"; + case UNW_VE_V43: + return "v43"; + case UNW_VE_V44: + return "v44"; + case UNW_VE_V45: + return "v45"; + case UNW_VE_V46: + return "v46"; + case UNW_VE_V47: + return "v47"; + case UNW_VE_V48: + return "v48"; + case UNW_VE_V49: + return "v49"; + case UNW_VE_V50: + return "v50"; + case UNW_VE_V51: + return "v51"; + case UNW_VE_V52: + return "v52"; + case UNW_VE_V53: + return "v53"; + case UNW_VE_V54: + return "v54"; + case UNW_VE_V55: + return "v55"; + case UNW_VE_V56: + return "v56"; + case UNW_VE_V57: + return "v57"; + case UNW_VE_V58: + return "v58"; + case UNW_VE_V59: + return "v59"; + case UNW_VE_V60: + return "v60"; + case UNW_VE_V61: + return "v61"; + case UNW_VE_V62: + return "v62"; + case UNW_VE_V63: + return "v63"; + case UNW_VE_VM0: + return "vm0"; + case UNW_VE_VM1: + return "vm1"; + case UNW_VE_VM2: + return "vm2"; + case UNW_VE_VM3: + return "vm3"; + case UNW_VE_VM4: + return "vm4"; + case UNW_VE_VM5: + return "vm5"; + case UNW_VE_VM6: + return "vm6"; + case UNW_VE_VM7: + return "vm7"; + case UNW_VE_VM8: + return "vm8"; + case UNW_VE_VM9: + return "vm9"; + case UNW_VE_VM10: + return "vm10"; + case UNW_VE_VM11: + return "vm11"; + case UNW_VE_VM12: + return "vm12"; + case UNW_VE_VM13: + return "vm13"; + case UNW_VE_VM14: + return "vm14"; + case UNW_VE_VM15: + return "vm15"; + } + return "unknown register"; +} +#endif // _LIBUNWIND_TARGET_VE + } // namespace libunwind #endif // __REGISTERS_HPP__ diff --git a/contrib/libs/libunwind/src/Unwind-sjlj.c b/contrib/libs/libunwind/src/Unwind-sjlj.c index 539f570568..d487995bb7 100644 --- a/contrib/libs/libunwind/src/Unwind-sjlj.c +++ b/contrib/libs/libunwind/src/Unwind-sjlj.c @@ -32,23 +32,23 @@ struct _Unwind_FunctionContext { // next function in stack of handlers struct _Unwind_FunctionContext *prev; -#if defined(__ve__) - // VE requires to store 64 bit pointers in the buffer for SjLj execption. - // We expand the size of values defined here. This size must be matched - // to the size returned by TargetMachine::getSjLjDataSize(). - +#if defined(__ve__) + // VE requires to store 64 bit pointers in the buffer for SjLj execption. + // We expand the size of values defined here. This size must be matched + // to the size returned by TargetMachine::getSjLjDataSize(). + + // set by calling function before registering to be the landing pad + uint64_t resumeLocation; + + // set by personality handler to be parameters passed to landing pad function + uint64_t resumeParameters[4]; +#else // set by calling function before registering to be the landing pad - uint64_t resumeLocation; - - // set by personality handler to be parameters passed to landing pad function - uint64_t resumeParameters[4]; -#else - // set by calling function before registering to be the landing pad uint32_t resumeLocation; // set by personality handler to be parameters passed to landing pad function uint32_t resumeParameters[4]; -#endif +#endif // set by calling function before registering _Unwind_Personality_Fn personality; // arm offset=24 diff --git a/contrib/libs/libunwind/src/UnwindCursor.hpp b/contrib/libs/libunwind/src/UnwindCursor.hpp index 4043552099..1ca842f33a 100644 --- a/contrib/libs/libunwind/src/UnwindCursor.hpp +++ b/contrib/libs/libunwind/src/UnwindCursor.hpp @@ -937,25 +937,25 @@ private: } #endif -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - bool setInfoForSigReturn() { - R dummy; - return setInfoForSigReturn(dummy); - } - int stepThroughSigReturn() { - R dummy; - return stepThroughSigReturn(dummy); - } - bool setInfoForSigReturn(Registers_arm64 &); - int stepThroughSigReturn(Registers_arm64 &); - template <typename Registers> bool setInfoForSigReturn(Registers &) { - return false; - } - template <typename Registers> int stepThroughSigReturn(Registers &) { - return UNW_STEP_END; - } -#endif - +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + bool setInfoForSigReturn() { + R dummy; + return setInfoForSigReturn(dummy); + } + int stepThroughSigReturn() { + R dummy; + return stepThroughSigReturn(dummy); + } + bool setInfoForSigReturn(Registers_arm64 &); + int stepThroughSigReturn(Registers_arm64 &); + template <typename Registers> bool setInfoForSigReturn(Registers &) { + return false; + } + template <typename Registers> int stepThroughSigReturn(Registers &) { + return UNW_STEP_END; + } +#endif + #if defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND) bool getInfoFromFdeCie(const typename CFI_Parser<A>::FDE_Info &fdeInfo, const typename CFI_Parser<A>::CIE_Info &cieInfo, @@ -1226,9 +1226,9 @@ private: unw_proc_info_t _info; bool _unwindInfoMissing; bool _isSignalFrame; -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - bool _isSigReturn = false; -#endif +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + bool _isSigReturn = false; +#endif }; @@ -1925,11 +1925,11 @@ bool UnwindCursor<A, R>::getInfoFromSEH(pint_t pc) { template <typename A, typename R> void UnwindCursor<A, R>::setInfoBasedOnIPRegister(bool isReturnAddress) { -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - _isSigReturn = false; -#endif - - pint_t pc = static_cast<pint_t>(this->getReg(UNW_REG_IP)); +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + _isSigReturn = false; +#endif + + pint_t pc = static_cast<pint_t>(this->getReg(UNW_REG_IP)); #if defined(_LIBUNWIND_ARM_EHABI) // Remove the thumb bit so the IP represents the actual instruction address. // This matches the behaviour of _Unwind_GetIP on arm. @@ -2027,78 +2027,78 @@ void UnwindCursor<A, R>::setInfoBasedOnIPRegister(bool isReturnAddress) { } #endif // #if defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND) -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - if (setInfoForSigReturn()) - return; -#endif - +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + if (setInfoForSigReturn()) + return; +#endif + // no unwind info, flag that we can't reliably unwind _unwindInfoMissing = true; } -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) +template <typename A, typename R> +bool UnwindCursor<A, R>::setInfoForSigReturn(Registers_arm64 &) { + // Look for the sigreturn trampoline. The trampoline's body is two + // specific instructions (see below). Typically the trampoline comes from the + // vDSO[1] (i.e. the __kernel_rt_sigreturn function). A libc might provide its + // own restorer function, though, or user-mode QEMU might write a trampoline + // onto the stack. + // + // This special code path is a fallback that is only used if the trampoline + // lacks proper (e.g. DWARF) unwind info. On AArch64, a new DWARF register + // constant for the PC needs to be defined before DWARF can handle a signal + // trampoline. This code may segfault if the target PC is unreadable, e.g.: + // - The PC points at a function compiled without unwind info, and which is + // part of an execute-only mapping (e.g. using -Wl,--execute-only). + // - The PC is invalid and happens to point to unreadable or unmapped memory. + // + // [1] https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/vdso/sigreturn.S + const pint_t pc = static_cast<pint_t>(this->getReg(UNW_REG_IP)); + // Look for instructions: mov x8, #0x8b; svc #0x0 + if (_addressSpace.get32(pc) == 0xd2801168 && + _addressSpace.get32(pc + 4) == 0xd4000001) { + _info = {}; + _isSigReturn = true; + return true; + } + return false; +} + template <typename A, typename R> -bool UnwindCursor<A, R>::setInfoForSigReturn(Registers_arm64 &) { - // Look for the sigreturn trampoline. The trampoline's body is two - // specific instructions (see below). Typically the trampoline comes from the - // vDSO[1] (i.e. the __kernel_rt_sigreturn function). A libc might provide its - // own restorer function, though, or user-mode QEMU might write a trampoline - // onto the stack. - // - // This special code path is a fallback that is only used if the trampoline - // lacks proper (e.g. DWARF) unwind info. On AArch64, a new DWARF register - // constant for the PC needs to be defined before DWARF can handle a signal - // trampoline. This code may segfault if the target PC is unreadable, e.g.: - // - The PC points at a function compiled without unwind info, and which is - // part of an execute-only mapping (e.g. using -Wl,--execute-only). - // - The PC is invalid and happens to point to unreadable or unmapped memory. - // - // [1] https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/vdso/sigreturn.S - const pint_t pc = static_cast<pint_t>(this->getReg(UNW_REG_IP)); - // Look for instructions: mov x8, #0x8b; svc #0x0 - if (_addressSpace.get32(pc) == 0xd2801168 && - _addressSpace.get32(pc + 4) == 0xd4000001) { - _info = {}; - _isSigReturn = true; - return true; - } - return false; -} - -template <typename A, typename R> -int UnwindCursor<A, R>::stepThroughSigReturn(Registers_arm64 &) { - // In the signal trampoline frame, sp points to an rt_sigframe[1], which is: - // - 128-byte siginfo struct - // - ucontext struct: - // - 8-byte long (uc_flags) - // - 8-byte pointer (uc_link) - // - 24-byte stack_t - // - 128-byte signal set - // - 8 bytes of padding because sigcontext has 16-byte alignment - // - sigcontext/mcontext_t - // [1] https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/signal.c - const pint_t kOffsetSpToSigcontext = (128 + 8 + 8 + 24 + 128 + 8); // 304 - - // Offsets from sigcontext to each register. - const pint_t kOffsetGprs = 8; // offset to "__u64 regs[31]" field - const pint_t kOffsetSp = 256; // offset to "__u64 sp" field - const pint_t kOffsetPc = 264; // offset to "__u64 pc" field - - pint_t sigctx = _registers.getSP() + kOffsetSpToSigcontext; - - for (int i = 0; i <= 30; ++i) { - uint64_t value = _addressSpace.get64(sigctx + kOffsetGprs + - static_cast<pint_t>(i * 8)); +int UnwindCursor<A, R>::stepThroughSigReturn(Registers_arm64 &) { + // In the signal trampoline frame, sp points to an rt_sigframe[1], which is: + // - 128-byte siginfo struct + // - ucontext struct: + // - 8-byte long (uc_flags) + // - 8-byte pointer (uc_link) + // - 24-byte stack_t + // - 128-byte signal set + // - 8 bytes of padding because sigcontext has 16-byte alignment + // - sigcontext/mcontext_t + // [1] https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/signal.c + const pint_t kOffsetSpToSigcontext = (128 + 8 + 8 + 24 + 128 + 8); // 304 + + // Offsets from sigcontext to each register. + const pint_t kOffsetGprs = 8; // offset to "__u64 regs[31]" field + const pint_t kOffsetSp = 256; // offset to "__u64 sp" field + const pint_t kOffsetPc = 264; // offset to "__u64 pc" field + + pint_t sigctx = _registers.getSP() + kOffsetSpToSigcontext; + + for (int i = 0; i <= 30; ++i) { + uint64_t value = _addressSpace.get64(sigctx + kOffsetGprs + + static_cast<pint_t>(i * 8)); _registers.setRegister(UNW_AARCH64_X0 + i, value); - } - _registers.setSP(_addressSpace.get64(sigctx + kOffsetSp)); - _registers.setIP(_addressSpace.get64(sigctx + kOffsetPc)); - _isSignalFrame = true; - return UNW_STEP_SUCCESS; -} -#endif // defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - -template <typename A, typename R> + } + _registers.setSP(_addressSpace.get64(sigctx + kOffsetSp)); + _registers.setIP(_addressSpace.get64(sigctx + kOffsetPc)); + _isSignalFrame = true; + return UNW_STEP_SUCCESS; +} +#endif // defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + +template <typename A, typename R> int UnwindCursor<A, R>::step() { // Bottom of stack is defined is when unwind info cannot be found. if (_unwindInfoMissing) @@ -2106,27 +2106,27 @@ int UnwindCursor<A, R>::step() { // Use unwinding info to modify register set as if function returned. int result; -#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) - if (_isSigReturn) { - result = this->stepThroughSigReturn(); - } else -#endif - { +#if defined(_LIBUNWIND_TARGET_LINUX) && defined(_LIBUNWIND_TARGET_AARCH64) + if (_isSigReturn) { + result = this->stepThroughSigReturn(); + } else +#endif + { #if defined(_LIBUNWIND_SUPPORT_COMPACT_UNWIND) - result = this->stepWithCompactEncoding(); + result = this->stepWithCompactEncoding(); #elif defined(_LIBUNWIND_SUPPORT_SEH_UNWIND) - result = this->stepWithSEHData(); + result = this->stepWithSEHData(); #elif defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND) - result = this->stepWithDwarfFDE(); + result = this->stepWithDwarfFDE(); #elif defined(_LIBUNWIND_ARM_EHABI) - result = this->stepWithEHABI(); + result = this->stepWithEHABI(); #else #error Need _LIBUNWIND_SUPPORT_COMPACT_UNWIND or \ _LIBUNWIND_SUPPORT_SEH_UNWIND or \ _LIBUNWIND_SUPPORT_DWARF_UNWIND or \ _LIBUNWIND_ARM_EHABI #endif - } + } // update info based on new PC if (result == UNW_STEP_SUCCESS) { diff --git a/contrib/libs/libunwind/src/UnwindRegistersRestore.S b/contrib/libs/libunwind/src/UnwindRegistersRestore.S index 4824be8ed9..1df97f5fc4 100644 --- a/contrib/libs/libunwind/src/UnwindRegistersRestore.S +++ b/contrib/libs/libunwind/src/UnwindRegistersRestore.S @@ -139,7 +139,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv) // load register (GPR) #define PPC64_LR(n) \ - ld n, (8 * (n + 2))(3) + ld n, (8 * (n + 2))(3) // restore integral registers // skip r0 for now @@ -181,12 +181,12 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv) // (note that this also restores floating point registers and V registers, // because part of VS is mapped to these registers) - addi 4, 3, PPC64_OFFS_FP + addi 4, 3, PPC64_OFFS_FP // load VS register #define PPC64_LVS(n) \ - lxvd2x n, 0, 4 ;\ - addi 4, 4, 16 + lxvd2x n, 0, 4 ;\ + addi 4, 4, 16 // restore the first 32 VS regs (and also all floating point regs) PPC64_LVS(0) @@ -225,23 +225,23 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv) // use VRSAVE to conditionally restore the remaining VS regs, // that are where the V regs are mapped - ld 5, PPC64_OFFS_VRSAVE(3) // test VRsave - cmpwi 5, 0 + ld 5, PPC64_OFFS_VRSAVE(3) // test VRsave + cmpwi 5, 0 beq Lnovec // conditionally load VS #define PPC64_CLVS_BOTTOM(n) \ beq Ldone##n ;\ - addi 4, 3, PPC64_OFFS_FP + n * 16 ;\ - lxvd2x n, 0, 4 ;\ + addi 4, 3, PPC64_OFFS_FP + n * 16 ;\ + lxvd2x n, 0, 4 ;\ Ldone##n: -#define PPC64_CLVSl(n) \ - andis. 0, 5, (1 PPC_LEFT_SHIFT(47-n)) ;\ +#define PPC64_CLVSl(n) \ + andis. 0, 5, (1 PPC_LEFT_SHIFT(47-n)) ;\ PPC64_CLVS_BOTTOM(n) -#define PPC64_CLVSh(n) \ - andi. 0, 5, (1 PPC_LEFT_SHIFT(63-n)) ;\ +#define PPC64_CLVSh(n) \ + andi. 0, 5, (1 PPC_LEFT_SHIFT(63-n)) ;\ PPC64_CLVS_BOTTOM(n) PPC64_CLVSl(32) @@ -281,7 +281,7 @@ PPC64_CLVS_BOTTOM(n) // load FP register #define PPC64_LF(n) \ - lfd n, (PPC64_OFFS_FP + n * 16)(3) + lfd n, (PPC64_OFFS_FP + n * 16)(3) // restore float registers PPC64_LF(0) @@ -319,30 +319,30 @@ PPC64_CLVS_BOTTOM(n) #if defined(__ALTIVEC__) // restore vector registers if any are in use - ld 5, PPC64_OFFS_VRSAVE(3) // test VRsave - cmpwi 5, 0 + ld 5, PPC64_OFFS_VRSAVE(3) // test VRsave + cmpwi 5, 0 beq Lnovec - subi 4, 1, 16 + subi 4, 1, 16 // r4 is now a 16-byte aligned pointer into the red zone // the _vectorScalarRegisters may not be 16-byte aligned // so copy via red zone temp buffer #define PPC64_CLV_UNALIGNED_BOTTOM(n) \ beq Ldone##n ;\ - ld 0, (PPC64_OFFS_V + n * 16)(3) ;\ - std 0, 0(4) ;\ - ld 0, (PPC64_OFFS_V + n * 16 + 8)(3) ;\ - std 0, 8(4) ;\ - lvx n, 0, 4 ;\ + ld 0, (PPC64_OFFS_V + n * 16)(3) ;\ + std 0, 0(4) ;\ + ld 0, (PPC64_OFFS_V + n * 16 + 8)(3) ;\ + std 0, 8(4) ;\ + lvx n, 0, 4 ;\ Ldone ## n: -#define PPC64_CLV_UNALIGNEDl(n) \ - andis. 0, 5, (1 PPC_LEFT_SHIFT(15-n)) ;\ +#define PPC64_CLV_UNALIGNEDl(n) \ + andis. 0, 5, (1 PPC_LEFT_SHIFT(15-n)) ;\ PPC64_CLV_UNALIGNED_BOTTOM(n) -#define PPC64_CLV_UNALIGNEDh(n) \ - andi. 0, 5, (1 PPC_LEFT_SHIFT(31-n)) ;\ +#define PPC64_CLV_UNALIGNEDh(n) \ + andi. 0, 5, (1 PPC_LEFT_SHIFT(31-n)) ;\ PPC64_CLV_UNALIGNED_BOTTOM(n) PPC64_CLV_UNALIGNEDl(0) @@ -382,10 +382,10 @@ PPC64_CLV_UNALIGNED_BOTTOM(n) #endif Lnovec: - ld 0, PPC64_OFFS_CR(3) - mtcr 0 - ld 0, PPC64_OFFS_SRR0(3) - mtctr 0 + ld 0, PPC64_OFFS_CR(3) + mtcr 0 + ld 0, PPC64_OFFS_SRR0(3) + mtctr 0 PPC64_LR(0) PPC64_LR(5) @@ -407,111 +407,111 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) // restore integral registerrs // skip r0 for now // skip r1 for now - lwz 2, 16(3) + lwz 2, 16(3) // skip r3 for now // skip r4 for now // skip r5 for now - lwz 6, 32(3) - lwz 7, 36(3) - lwz 8, 40(3) - lwz 9, 44(3) - lwz 10, 48(3) - lwz 11, 52(3) - lwz 12, 56(3) - lwz 13, 60(3) - lwz 14, 64(3) - lwz 15, 68(3) - lwz 16, 72(3) - lwz 17, 76(3) - lwz 18, 80(3) - lwz 19, 84(3) - lwz 20, 88(3) - lwz 21, 92(3) - lwz 22, 96(3) - lwz 23,100(3) - lwz 24,104(3) - lwz 25,108(3) - lwz 26,112(3) - lwz 27,116(3) - lwz 28,120(3) - lwz 29,124(3) - lwz 30,128(3) - lwz 31,132(3) + lwz 6, 32(3) + lwz 7, 36(3) + lwz 8, 40(3) + lwz 9, 44(3) + lwz 10, 48(3) + lwz 11, 52(3) + lwz 12, 56(3) + lwz 13, 60(3) + lwz 14, 64(3) + lwz 15, 68(3) + lwz 16, 72(3) + lwz 17, 76(3) + lwz 18, 80(3) + lwz 19, 84(3) + lwz 20, 88(3) + lwz 21, 92(3) + lwz 22, 96(3) + lwz 23,100(3) + lwz 24,104(3) + lwz 25,108(3) + lwz 26,112(3) + lwz 27,116(3) + lwz 28,120(3) + lwz 29,124(3) + lwz 30,128(3) + lwz 31,132(3) #ifndef __NO_FPRS__ // restore float registers - lfd 0, 160(3) - lfd 1, 168(3) - lfd 2, 176(3) - lfd 3, 184(3) - lfd 4, 192(3) - lfd 5, 200(3) - lfd 6, 208(3) - lfd 7, 216(3) - lfd 8, 224(3) - lfd 9, 232(3) - lfd 10,240(3) - lfd 11,248(3) - lfd 12,256(3) - lfd 13,264(3) - lfd 14,272(3) - lfd 15,280(3) - lfd 16,288(3) - lfd 17,296(3) - lfd 18,304(3) - lfd 19,312(3) - lfd 20,320(3) - lfd 21,328(3) - lfd 22,336(3) - lfd 23,344(3) - lfd 24,352(3) - lfd 25,360(3) - lfd 26,368(3) - lfd 27,376(3) - lfd 28,384(3) - lfd 29,392(3) - lfd 30,400(3) - lfd 31,408(3) + lfd 0, 160(3) + lfd 1, 168(3) + lfd 2, 176(3) + lfd 3, 184(3) + lfd 4, 192(3) + lfd 5, 200(3) + lfd 6, 208(3) + lfd 7, 216(3) + lfd 8, 224(3) + lfd 9, 232(3) + lfd 10,240(3) + lfd 11,248(3) + lfd 12,256(3) + lfd 13,264(3) + lfd 14,272(3) + lfd 15,280(3) + lfd 16,288(3) + lfd 17,296(3) + lfd 18,304(3) + lfd 19,312(3) + lfd 20,320(3) + lfd 21,328(3) + lfd 22,336(3) + lfd 23,344(3) + lfd 24,352(3) + lfd 25,360(3) + lfd 26,368(3) + lfd 27,376(3) + lfd 28,384(3) + lfd 29,392(3) + lfd 30,400(3) + lfd 31,408(3) #endif #if defined(__ALTIVEC__) // restore vector registers if any are in use - lwz 5, 156(3) // test VRsave - cmpwi 5, 0 + lwz 5, 156(3) // test VRsave + cmpwi 5, 0 beq Lnovec - subi 4, 1, 16 - rlwinm 4, 4, 0, 0, 27 // mask low 4-bits + subi 4, 1, 16 + rlwinm 4, 4, 0, 0, 27 // mask low 4-bits // r4 is now a 16-byte aligned pointer into the red zone // the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer - -#define LOAD_VECTOR_UNALIGNEDl(_index) \ - andis. 0, 5, (1 PPC_LEFT_SHIFT(15-_index)) SEPARATOR \ + +#define LOAD_VECTOR_UNALIGNEDl(_index) \ + andis. 0, 5, (1 PPC_LEFT_SHIFT(15-_index)) SEPARATOR \ beq Ldone ## _index SEPARATOR \ - lwz 0, 424+_index*16(3) SEPARATOR \ - stw 0, 0(%r4) SEPARATOR \ - lwz 0, 424+_index*16+4(%r3) SEPARATOR \ - stw 0, 4(%r4) SEPARATOR \ - lwz 0, 424+_index*16+8(%r3) SEPARATOR \ - stw 0, 8(%r4) SEPARATOR \ - lwz 0, 424+_index*16+12(%r3) SEPARATOR \ - stw 0, 12(%r4) SEPARATOR \ - lvx _index, 0, 4 SEPARATOR \ + lwz 0, 424+_index*16(3) SEPARATOR \ + stw 0, 0(%r4) SEPARATOR \ + lwz 0, 424+_index*16+4(%r3) SEPARATOR \ + stw 0, 4(%r4) SEPARATOR \ + lwz 0, 424+_index*16+8(%r3) SEPARATOR \ + stw 0, 8(%r4) SEPARATOR \ + lwz 0, 424+_index*16+12(%r3) SEPARATOR \ + stw 0, 12(%r4) SEPARATOR \ + lvx _index, 0, 4 SEPARATOR \ Ldone ## _index: -#define LOAD_VECTOR_UNALIGNEDh(_index) \ - andi. 0, 5, (1 PPC_LEFT_SHIFT(31-_index)) SEPARATOR \ +#define LOAD_VECTOR_UNALIGNEDh(_index) \ + andi. 0, 5, (1 PPC_LEFT_SHIFT(31-_index)) SEPARATOR \ beq Ldone ## _index SEPARATOR \ - lwz 0, 424+_index*16(3) SEPARATOR \ - stw 0, 0(4) SEPARATOR \ - lwz 0, 424+_index*16+4(3) SEPARATOR \ - stw 0, 4(4) SEPARATOR \ - lwz 0, 424+_index*16+8(3) SEPARATOR \ - stw 0, 8(%r4) SEPARATOR \ - lwz 0, 424+_index*16+12(3) SEPARATOR \ - stw 0, 12(4) SEPARATOR \ - lvx _index, 0, 4 SEPARATOR \ + lwz 0, 424+_index*16(3) SEPARATOR \ + stw 0, 0(4) SEPARATOR \ + lwz 0, 424+_index*16+4(3) SEPARATOR \ + stw 0, 4(4) SEPARATOR \ + lwz 0, 424+_index*16+8(3) SEPARATOR \ + stw 0, 8(%r4) SEPARATOR \ + lwz 0, 424+_index*16+12(3) SEPARATOR \ + stw 0, 12(4) SEPARATOR \ + lvx _index, 0, 4 SEPARATOR \ Ldone ## _index: @@ -550,17 +550,17 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) #endif Lnovec: - lwz 0, 136(3) // __cr - mtcr 0 - lwz 0, 148(3) // __ctr - mtctr 0 - lwz 0, 0(3) // __ssr0 - mtctr 0 - lwz 0, 8(3) // do r0 now - lwz 5, 28(3) // do r5 now - lwz 4, 24(3) // do r4 now - lwz 1, 12(3) // do sp now - lwz 3, 20(3) // do r3 last + lwz 0, 136(3) // __cr + mtcr 0 + lwz 0, 148(3) // __ctr + mtctr 0 + lwz 0, 0(3) // __ssr0 + mtctr 0 + lwz 0, 8(3) // do r0 now + lwz 5, 28(3) // do r5 now + lwz 4, 24(3) // do r4 now + lwz 1, 12(3) // do sp now + lwz 3, 20(3) // do r3 last bctr #elif defined(__aarch64__) @@ -1131,7 +1131,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv) jmp %o7 nop -#elif defined(__riscv) +#elif defined(__riscv) // // void libunwind::Registers_riscv::jumpto() @@ -1141,74 +1141,74 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_sparc6jumptoEv) // .p2align 2 DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv) -# if defined(__riscv_flen) - FLOAD f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0) - FLOAD f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0) - FLOAD f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0) - FLOAD f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0) - FLOAD f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0) - FLOAD f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0) - FLOAD f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0) - FLOAD f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0) - FLOAD f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0) - FLOAD f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0) - FLOAD f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0) - FLOAD f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0) - FLOAD f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0) - FLOAD f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0) - FLOAD f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0) - FLOAD f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0) - FLOAD f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0) - FLOAD f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0) - FLOAD f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0) - FLOAD f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0) - FLOAD f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0) - FLOAD f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0) - FLOAD f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0) - FLOAD f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0) - FLOAD f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0) - FLOAD f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0) - FLOAD f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0) - FLOAD f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0) - FLOAD f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0) - FLOAD f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0) - FLOAD f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0) - FLOAD f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0) -# endif +# if defined(__riscv_flen) + FLOAD f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0) + FLOAD f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0) + FLOAD f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0) + FLOAD f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0) + FLOAD f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0) + FLOAD f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0) + FLOAD f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0) + FLOAD f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0) + FLOAD f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0) + FLOAD f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0) + FLOAD f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0) + FLOAD f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0) + FLOAD f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0) + FLOAD f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0) + FLOAD f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0) + FLOAD f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0) + FLOAD f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0) + FLOAD f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0) + FLOAD f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0) + FLOAD f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0) + FLOAD f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0) + FLOAD f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0) + FLOAD f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0) + FLOAD f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0) + FLOAD f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0) + FLOAD f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0) + FLOAD f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0) + FLOAD f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0) + FLOAD f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0) + FLOAD f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0) + FLOAD f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0) + FLOAD f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0) +# endif // x0 is zero - ILOAD x1, (RISCV_ISIZE * 0)(a0) // restore pc into ra - ILOAD x2, (RISCV_ISIZE * 2)(a0) - ILOAD x3, (RISCV_ISIZE * 3)(a0) - ILOAD x4, (RISCV_ISIZE * 4)(a0) - ILOAD x5, (RISCV_ISIZE * 5)(a0) - ILOAD x6, (RISCV_ISIZE * 6)(a0) - ILOAD x7, (RISCV_ISIZE * 7)(a0) - ILOAD x8, (RISCV_ISIZE * 8)(a0) - ILOAD x9, (RISCV_ISIZE * 9)(a0) + ILOAD x1, (RISCV_ISIZE * 0)(a0) // restore pc into ra + ILOAD x2, (RISCV_ISIZE * 2)(a0) + ILOAD x3, (RISCV_ISIZE * 3)(a0) + ILOAD x4, (RISCV_ISIZE * 4)(a0) + ILOAD x5, (RISCV_ISIZE * 5)(a0) + ILOAD x6, (RISCV_ISIZE * 6)(a0) + ILOAD x7, (RISCV_ISIZE * 7)(a0) + ILOAD x8, (RISCV_ISIZE * 8)(a0) + ILOAD x9, (RISCV_ISIZE * 9)(a0) // skip a0 for now - ILOAD x11, (RISCV_ISIZE * 11)(a0) - ILOAD x12, (RISCV_ISIZE * 12)(a0) - ILOAD x13, (RISCV_ISIZE * 13)(a0) - ILOAD x14, (RISCV_ISIZE * 14)(a0) - ILOAD x15, (RISCV_ISIZE * 15)(a0) - ILOAD x16, (RISCV_ISIZE * 16)(a0) - ILOAD x17, (RISCV_ISIZE * 17)(a0) - ILOAD x18, (RISCV_ISIZE * 18)(a0) - ILOAD x19, (RISCV_ISIZE * 19)(a0) - ILOAD x20, (RISCV_ISIZE * 20)(a0) - ILOAD x21, (RISCV_ISIZE * 21)(a0) - ILOAD x22, (RISCV_ISIZE * 22)(a0) - ILOAD x23, (RISCV_ISIZE * 23)(a0) - ILOAD x24, (RISCV_ISIZE * 24)(a0) - ILOAD x25, (RISCV_ISIZE * 25)(a0) - ILOAD x26, (RISCV_ISIZE * 26)(a0) - ILOAD x27, (RISCV_ISIZE * 27)(a0) - ILOAD x28, (RISCV_ISIZE * 28)(a0) - ILOAD x29, (RISCV_ISIZE * 29)(a0) - ILOAD x30, (RISCV_ISIZE * 30)(a0) - ILOAD x31, (RISCV_ISIZE * 31)(a0) - ILOAD x10, (RISCV_ISIZE * 10)(a0) // restore a0 + ILOAD x11, (RISCV_ISIZE * 11)(a0) + ILOAD x12, (RISCV_ISIZE * 12)(a0) + ILOAD x13, (RISCV_ISIZE * 13)(a0) + ILOAD x14, (RISCV_ISIZE * 14)(a0) + ILOAD x15, (RISCV_ISIZE * 15)(a0) + ILOAD x16, (RISCV_ISIZE * 16)(a0) + ILOAD x17, (RISCV_ISIZE * 17)(a0) + ILOAD x18, (RISCV_ISIZE * 18)(a0) + ILOAD x19, (RISCV_ISIZE * 19)(a0) + ILOAD x20, (RISCV_ISIZE * 20)(a0) + ILOAD x21, (RISCV_ISIZE * 21)(a0) + ILOAD x22, (RISCV_ISIZE * 22)(a0) + ILOAD x23, (RISCV_ISIZE * 23)(a0) + ILOAD x24, (RISCV_ISIZE * 24)(a0) + ILOAD x25, (RISCV_ISIZE * 25)(a0) + ILOAD x26, (RISCV_ISIZE * 26)(a0) + ILOAD x27, (RISCV_ISIZE * 27)(a0) + ILOAD x28, (RISCV_ISIZE * 28)(a0) + ILOAD x29, (RISCV_ISIZE * 29)(a0) + ILOAD x30, (RISCV_ISIZE * 30)(a0) + ILOAD x31, (RISCV_ISIZE * 31)(a0) + ILOAD x10, (RISCV_ISIZE * 10)(a0) // restore a0 ret // jump to ra diff --git a/contrib/libs/libunwind/src/UnwindRegistersSave.S b/contrib/libs/libunwind/src/UnwindRegistersSave.S index ce118914b0..9566bb0335 100644 --- a/contrib/libs/libunwind/src/UnwindRegistersSave.S +++ b/contrib/libs/libunwind/src/UnwindRegistersSave.S @@ -338,12 +338,12 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) // store register (GPR) #define PPC64_STR(n) \ - std n, (8 * (n + 2))(3) + std n, (8 * (n + 2))(3) // save GPRs PPC64_STR(0) - mflr 0 - std 0, PPC64_OFFS_SRR0(3) // store lr as ssr0 + mflr 0 + std 0, PPC64_OFFS_SRR0(3) // store lr as ssr0 PPC64_STR(1) PPC64_STR(2) PPC64_STR(3) @@ -376,28 +376,28 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) PPC64_STR(30) PPC64_STR(31) - mfcr 0 - std 0, PPC64_OFFS_CR(3) - mfxer 0 - std 0, PPC64_OFFS_XER(3) - mflr 0 - std 0, PPC64_OFFS_LR(3) - mfctr 0 - std 0, PPC64_OFFS_CTR(3) - mfvrsave 0 - std 0, PPC64_OFFS_VRSAVE(3) + mfcr 0 + std 0, PPC64_OFFS_CR(3) + mfxer 0 + std 0, PPC64_OFFS_XER(3) + mflr 0 + std 0, PPC64_OFFS_LR(3) + mfctr 0 + std 0, PPC64_OFFS_CTR(3) + mfvrsave 0 + std 0, PPC64_OFFS_VRSAVE(3) #if defined(__VSX__) // save VS registers // (note that this also saves floating point registers and V registers, // because part of VS is mapped to these registers) - addi 4, 3, PPC64_OFFS_FP + addi 4, 3, PPC64_OFFS_FP // store VS register #define PPC64_STVS(n) \ - stxvd2x n, 0, 4 ;\ - addi 4, 4, 16 + stxvd2x n, 0, 4 ;\ + addi 4, 4, 16 PPC64_STVS(0) PPC64_STVS(1) @@ -468,7 +468,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) // store FP register #define PPC64_STF(n) \ - stfd n, (PPC64_OFFS_FP + n * 16)(3) + stfd n, (PPC64_OFFS_FP + n * 16)(3) // save float registers PPC64_STF(0) @@ -510,14 +510,14 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) // Use 16-bytes below the stack pointer as an // aligned buffer to save each vector register. // Note that the stack pointer is always 16-byte aligned. - subi 4, 1, 16 + subi 4, 1, 16 -#define PPC64_STV_UNALIGNED(n) \ - stvx n, 0, 4 ;\ - ld 5, 0(4) ;\ - std 5, (PPC64_OFFS_V + n * 16)(3) ;\ - ld 5, 8(4) ;\ - std 5, (PPC64_OFFS_V + n * 16 + 8)(3) +#define PPC64_STV_UNALIGNED(n) \ + stvx n, 0, 4 ;\ + ld 5, 0(4) ;\ + std 5, (PPC64_OFFS_V + n * 16)(3) ;\ + ld 5, 8(4) ;\ + std 5, (PPC64_OFFS_V + n * 16 + 8)(3) PPC64_STV_UNALIGNED(0) PPC64_STV_UNALIGNED(1) @@ -555,7 +555,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) #endif #endif - li 3, 0 // return UNW_ESUCCESS + li 3, 0 // return UNW_ESUCCESS blr @@ -568,140 +568,140 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) // thread_state pointer is in r3 // DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) - stw 0, 8(3) - mflr 0 - stw 0, 0(3) // store lr as ssr0 - stw 1, 12(3) - stw 2, 16(3) - stw 3, 20(3) - stw 4, 24(3) - stw 5, 28(3) - stw 6, 32(3) - stw 7, 36(3) - stw 8, 40(3) - stw 9, 44(3) - stw 10, 48(3) - stw 11, 52(3) - stw 12, 56(3) - stw 13, 60(3) - stw 14, 64(3) - stw 15, 68(3) - stw 16, 72(3) - stw 17, 76(3) - stw 18, 80(3) - stw 19, 84(3) - stw 20, 88(3) - stw 21, 92(3) - stw 22, 96(3) - stw 23,100(3) - stw 24,104(3) - stw 25,108(3) - stw 26,112(3) - stw 27,116(3) - stw 28,120(3) - stw 29,124(3) - stw 30,128(3) - stw 31,132(3) + stw 0, 8(3) + mflr 0 + stw 0, 0(3) // store lr as ssr0 + stw 1, 12(3) + stw 2, 16(3) + stw 3, 20(3) + stw 4, 24(3) + stw 5, 28(3) + stw 6, 32(3) + stw 7, 36(3) + stw 8, 40(3) + stw 9, 44(3) + stw 10, 48(3) + stw 11, 52(3) + stw 12, 56(3) + stw 13, 60(3) + stw 14, 64(3) + stw 15, 68(3) + stw 16, 72(3) + stw 17, 76(3) + stw 18, 80(3) + stw 19, 84(3) + stw 20, 88(3) + stw 21, 92(3) + stw 22, 96(3) + stw 23,100(3) + stw 24,104(3) + stw 25,108(3) + stw 26,112(3) + stw 27,116(3) + stw 28,120(3) + stw 29,124(3) + stw 30,128(3) + stw 31,132(3) // save VRSave register - mfspr 0, 256 - stw 0, 156(3) + mfspr 0, 256 + stw 0, 156(3) // save CR registers - mfcr 0 - stw 0, 136(3) + mfcr 0 + stw 0, 136(3) // save CTR register - mfctr 0 - stw 0, 148(3) + mfctr 0 + stw 0, 148(3) #if !defined(__NO_FPRS__) // save float registers - stfd 0, 160(3) - stfd 1, 168(3) - stfd 2, 176(3) - stfd 3, 184(3) - stfd 4, 192(3) - stfd 5, 200(3) - stfd 6, 208(3) - stfd 7, 216(3) - stfd 8, 224(3) - stfd 9, 232(3) - stfd 10,240(3) - stfd 11,248(3) - stfd 12,256(3) - stfd 13,264(3) - stfd 14,272(3) - stfd 15,280(3) - stfd 16,288(3) - stfd 17,296(3) - stfd 18,304(3) - stfd 19,312(3) - stfd 20,320(3) - stfd 21,328(3) - stfd 22,336(3) - stfd 23,344(3) - stfd 24,352(3) - stfd 25,360(3) - stfd 26,368(3) - stfd 27,376(3) - stfd 28,384(3) - stfd 29,392(3) - stfd 30,400(3) - stfd 31,408(3) + stfd 0, 160(3) + stfd 1, 168(3) + stfd 2, 176(3) + stfd 3, 184(3) + stfd 4, 192(3) + stfd 5, 200(3) + stfd 6, 208(3) + stfd 7, 216(3) + stfd 8, 224(3) + stfd 9, 232(3) + stfd 10,240(3) + stfd 11,248(3) + stfd 12,256(3) + stfd 13,264(3) + stfd 14,272(3) + stfd 15,280(3) + stfd 16,288(3) + stfd 17,296(3) + stfd 18,304(3) + stfd 19,312(3) + stfd 20,320(3) + stfd 21,328(3) + stfd 22,336(3) + stfd 23,344(3) + stfd 24,352(3) + stfd 25,360(3) + stfd 26,368(3) + stfd 27,376(3) + stfd 28,384(3) + stfd 29,392(3) + stfd 30,400(3) + stfd 31,408(3) #endif #if defined(__ALTIVEC__) // save vector registers - subi 4, 1, 16 - rlwinm 4, 4, 0, 0, 27 // mask low 4-bits + subi 4, 1, 16 + rlwinm 4, 4, 0, 0, 27 // mask low 4-bits // r4 is now a 16-byte aligned pointer into the red zone #define SAVE_VECTOR_UNALIGNED(_vec, _offset) \ - stvx _vec, 0, 4 SEPARATOR \ - lwz 5, 0(4) SEPARATOR \ - stw 5, _offset(3) SEPARATOR \ - lwz 5, 4(4) SEPARATOR \ - stw 5, _offset+4(3) SEPARATOR \ - lwz 5, 8(4) SEPARATOR \ - stw 5, _offset+8(3) SEPARATOR \ - lwz 5, 12(4) SEPARATOR \ - stw 5, _offset+12(3) - - SAVE_VECTOR_UNALIGNED( 0, 424+0x000) - SAVE_VECTOR_UNALIGNED( 1, 424+0x010) - SAVE_VECTOR_UNALIGNED( 2, 424+0x020) - SAVE_VECTOR_UNALIGNED( 3, 424+0x030) - SAVE_VECTOR_UNALIGNED( 4, 424+0x040) - SAVE_VECTOR_UNALIGNED( 5, 424+0x050) - SAVE_VECTOR_UNALIGNED( 6, 424+0x060) - SAVE_VECTOR_UNALIGNED( 7, 424+0x070) - SAVE_VECTOR_UNALIGNED( 8, 424+0x080) - SAVE_VECTOR_UNALIGNED( 9, 424+0x090) - SAVE_VECTOR_UNALIGNED(10, 424+0x0A0) - SAVE_VECTOR_UNALIGNED(11, 424+0x0B0) - SAVE_VECTOR_UNALIGNED(12, 424+0x0C0) - SAVE_VECTOR_UNALIGNED(13, 424+0x0D0) - SAVE_VECTOR_UNALIGNED(14, 424+0x0E0) - SAVE_VECTOR_UNALIGNED(15, 424+0x0F0) - SAVE_VECTOR_UNALIGNED(16, 424+0x100) - SAVE_VECTOR_UNALIGNED(17, 424+0x110) - SAVE_VECTOR_UNALIGNED(18, 424+0x120) - SAVE_VECTOR_UNALIGNED(19, 424+0x130) - SAVE_VECTOR_UNALIGNED(20, 424+0x140) - SAVE_VECTOR_UNALIGNED(21, 424+0x150) - SAVE_VECTOR_UNALIGNED(22, 424+0x160) - SAVE_VECTOR_UNALIGNED(23, 424+0x170) - SAVE_VECTOR_UNALIGNED(24, 424+0x180) - SAVE_VECTOR_UNALIGNED(25, 424+0x190) - SAVE_VECTOR_UNALIGNED(26, 424+0x1A0) - SAVE_VECTOR_UNALIGNED(27, 424+0x1B0) - SAVE_VECTOR_UNALIGNED(28, 424+0x1C0) - SAVE_VECTOR_UNALIGNED(29, 424+0x1D0) - SAVE_VECTOR_UNALIGNED(30, 424+0x1E0) - SAVE_VECTOR_UNALIGNED(31, 424+0x1F0) + stvx _vec, 0, 4 SEPARATOR \ + lwz 5, 0(4) SEPARATOR \ + stw 5, _offset(3) SEPARATOR \ + lwz 5, 4(4) SEPARATOR \ + stw 5, _offset+4(3) SEPARATOR \ + lwz 5, 8(4) SEPARATOR \ + stw 5, _offset+8(3) SEPARATOR \ + lwz 5, 12(4) SEPARATOR \ + stw 5, _offset+12(3) + + SAVE_VECTOR_UNALIGNED( 0, 424+0x000) + SAVE_VECTOR_UNALIGNED( 1, 424+0x010) + SAVE_VECTOR_UNALIGNED( 2, 424+0x020) + SAVE_VECTOR_UNALIGNED( 3, 424+0x030) + SAVE_VECTOR_UNALIGNED( 4, 424+0x040) + SAVE_VECTOR_UNALIGNED( 5, 424+0x050) + SAVE_VECTOR_UNALIGNED( 6, 424+0x060) + SAVE_VECTOR_UNALIGNED( 7, 424+0x070) + SAVE_VECTOR_UNALIGNED( 8, 424+0x080) + SAVE_VECTOR_UNALIGNED( 9, 424+0x090) + SAVE_VECTOR_UNALIGNED(10, 424+0x0A0) + SAVE_VECTOR_UNALIGNED(11, 424+0x0B0) + SAVE_VECTOR_UNALIGNED(12, 424+0x0C0) + SAVE_VECTOR_UNALIGNED(13, 424+0x0D0) + SAVE_VECTOR_UNALIGNED(14, 424+0x0E0) + SAVE_VECTOR_UNALIGNED(15, 424+0x0F0) + SAVE_VECTOR_UNALIGNED(16, 424+0x100) + SAVE_VECTOR_UNALIGNED(17, 424+0x110) + SAVE_VECTOR_UNALIGNED(18, 424+0x120) + SAVE_VECTOR_UNALIGNED(19, 424+0x130) + SAVE_VECTOR_UNALIGNED(20, 424+0x140) + SAVE_VECTOR_UNALIGNED(21, 424+0x150) + SAVE_VECTOR_UNALIGNED(22, 424+0x160) + SAVE_VECTOR_UNALIGNED(23, 424+0x170) + SAVE_VECTOR_UNALIGNED(24, 424+0x180) + SAVE_VECTOR_UNALIGNED(25, 424+0x190) + SAVE_VECTOR_UNALIGNED(26, 424+0x1A0) + SAVE_VECTOR_UNALIGNED(27, 424+0x1B0) + SAVE_VECTOR_UNALIGNED(28, 424+0x1C0) + SAVE_VECTOR_UNALIGNED(29, 424+0x1D0) + SAVE_VECTOR_UNALIGNED(30, 424+0x1E0) + SAVE_VECTOR_UNALIGNED(31, 424+0x1F0) #endif - li 3, 0 // return UNW_ESUCCESS + li 3, 0 // return UNW_ESUCCESS blr @@ -1087,7 +1087,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) jmp %o7 clr %o0 // return UNW_ESUCCESS -#elif defined(__riscv) +#elif defined(__riscv) # # extern int __unw_getcontext(unw_context_t* thread_state) @@ -1096,73 +1096,73 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) # thread_state pointer is in a0 # DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext) - ISTORE x1, (RISCV_ISIZE * 0)(a0) // store ra as pc - ISTORE x1, (RISCV_ISIZE * 1)(a0) - ISTORE x2, (RISCV_ISIZE * 2)(a0) - ISTORE x3, (RISCV_ISIZE * 3)(a0) - ISTORE x4, (RISCV_ISIZE * 4)(a0) - ISTORE x5, (RISCV_ISIZE * 5)(a0) - ISTORE x6, (RISCV_ISIZE * 6)(a0) - ISTORE x7, (RISCV_ISIZE * 7)(a0) - ISTORE x8, (RISCV_ISIZE * 8)(a0) - ISTORE x9, (RISCV_ISIZE * 9)(a0) - ISTORE x10, (RISCV_ISIZE * 10)(a0) - ISTORE x11, (RISCV_ISIZE * 11)(a0) - ISTORE x12, (RISCV_ISIZE * 12)(a0) - ISTORE x13, (RISCV_ISIZE * 13)(a0) - ISTORE x14, (RISCV_ISIZE * 14)(a0) - ISTORE x15, (RISCV_ISIZE * 15)(a0) - ISTORE x16, (RISCV_ISIZE * 16)(a0) - ISTORE x17, (RISCV_ISIZE * 17)(a0) - ISTORE x18, (RISCV_ISIZE * 18)(a0) - ISTORE x19, (RISCV_ISIZE * 19)(a0) - ISTORE x20, (RISCV_ISIZE * 20)(a0) - ISTORE x21, (RISCV_ISIZE * 21)(a0) - ISTORE x22, (RISCV_ISIZE * 22)(a0) - ISTORE x23, (RISCV_ISIZE * 23)(a0) - ISTORE x24, (RISCV_ISIZE * 24)(a0) - ISTORE x25, (RISCV_ISIZE * 25)(a0) - ISTORE x26, (RISCV_ISIZE * 26)(a0) - ISTORE x27, (RISCV_ISIZE * 27)(a0) - ISTORE x28, (RISCV_ISIZE * 28)(a0) - ISTORE x29, (RISCV_ISIZE * 29)(a0) - ISTORE x30, (RISCV_ISIZE * 30)(a0) - ISTORE x31, (RISCV_ISIZE * 31)(a0) - -# if defined(__riscv_flen) - FSTORE f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0) - FSTORE f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0) - FSTORE f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0) - FSTORE f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0) - FSTORE f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0) - FSTORE f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0) - FSTORE f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0) - FSTORE f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0) - FSTORE f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0) - FSTORE f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0) - FSTORE f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0) - FSTORE f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0) - FSTORE f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0) - FSTORE f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0) - FSTORE f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0) - FSTORE f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0) - FSTORE f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0) - FSTORE f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0) - FSTORE f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0) - FSTORE f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0) - FSTORE f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0) - FSTORE f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0) - FSTORE f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0) - FSTORE f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0) - FSTORE f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0) - FSTORE f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0) - FSTORE f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0) - FSTORE f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0) - FSTORE f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0) - FSTORE f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0) - FSTORE f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0) - FSTORE f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0) -# endif + ISTORE x1, (RISCV_ISIZE * 0)(a0) // store ra as pc + ISTORE x1, (RISCV_ISIZE * 1)(a0) + ISTORE x2, (RISCV_ISIZE * 2)(a0) + ISTORE x3, (RISCV_ISIZE * 3)(a0) + ISTORE x4, (RISCV_ISIZE * 4)(a0) + ISTORE x5, (RISCV_ISIZE * 5)(a0) + ISTORE x6, (RISCV_ISIZE * 6)(a0) + ISTORE x7, (RISCV_ISIZE * 7)(a0) + ISTORE x8, (RISCV_ISIZE * 8)(a0) + ISTORE x9, (RISCV_ISIZE * 9)(a0) + ISTORE x10, (RISCV_ISIZE * 10)(a0) + ISTORE x11, (RISCV_ISIZE * 11)(a0) + ISTORE x12, (RISCV_ISIZE * 12)(a0) + ISTORE x13, (RISCV_ISIZE * 13)(a0) + ISTORE x14, (RISCV_ISIZE * 14)(a0) + ISTORE x15, (RISCV_ISIZE * 15)(a0) + ISTORE x16, (RISCV_ISIZE * 16)(a0) + ISTORE x17, (RISCV_ISIZE * 17)(a0) + ISTORE x18, (RISCV_ISIZE * 18)(a0) + ISTORE x19, (RISCV_ISIZE * 19)(a0) + ISTORE x20, (RISCV_ISIZE * 20)(a0) + ISTORE x21, (RISCV_ISIZE * 21)(a0) + ISTORE x22, (RISCV_ISIZE * 22)(a0) + ISTORE x23, (RISCV_ISIZE * 23)(a0) + ISTORE x24, (RISCV_ISIZE * 24)(a0) + ISTORE x25, (RISCV_ISIZE * 25)(a0) + ISTORE x26, (RISCV_ISIZE * 26)(a0) + ISTORE x27, (RISCV_ISIZE * 27)(a0) + ISTORE x28, (RISCV_ISIZE * 28)(a0) + ISTORE x29, (RISCV_ISIZE * 29)(a0) + ISTORE x30, (RISCV_ISIZE * 30)(a0) + ISTORE x31, (RISCV_ISIZE * 31)(a0) + +# if defined(__riscv_flen) + FSTORE f0, (RISCV_FOFFSET + RISCV_FSIZE * 0)(a0) + FSTORE f1, (RISCV_FOFFSET + RISCV_FSIZE * 1)(a0) + FSTORE f2, (RISCV_FOFFSET + RISCV_FSIZE * 2)(a0) + FSTORE f3, (RISCV_FOFFSET + RISCV_FSIZE * 3)(a0) + FSTORE f4, (RISCV_FOFFSET + RISCV_FSIZE * 4)(a0) + FSTORE f5, (RISCV_FOFFSET + RISCV_FSIZE * 5)(a0) + FSTORE f6, (RISCV_FOFFSET + RISCV_FSIZE * 6)(a0) + FSTORE f7, (RISCV_FOFFSET + RISCV_FSIZE * 7)(a0) + FSTORE f8, (RISCV_FOFFSET + RISCV_FSIZE * 8)(a0) + FSTORE f9, (RISCV_FOFFSET + RISCV_FSIZE * 9)(a0) + FSTORE f10, (RISCV_FOFFSET + RISCV_FSIZE * 10)(a0) + FSTORE f11, (RISCV_FOFFSET + RISCV_FSIZE * 11)(a0) + FSTORE f12, (RISCV_FOFFSET + RISCV_FSIZE * 12)(a0) + FSTORE f13, (RISCV_FOFFSET + RISCV_FSIZE * 13)(a0) + FSTORE f14, (RISCV_FOFFSET + RISCV_FSIZE * 14)(a0) + FSTORE f15, (RISCV_FOFFSET + RISCV_FSIZE * 15)(a0) + FSTORE f16, (RISCV_FOFFSET + RISCV_FSIZE * 16)(a0) + FSTORE f17, (RISCV_FOFFSET + RISCV_FSIZE * 17)(a0) + FSTORE f18, (RISCV_FOFFSET + RISCV_FSIZE * 18)(a0) + FSTORE f19, (RISCV_FOFFSET + RISCV_FSIZE * 19)(a0) + FSTORE f20, (RISCV_FOFFSET + RISCV_FSIZE * 20)(a0) + FSTORE f21, (RISCV_FOFFSET + RISCV_FSIZE * 21)(a0) + FSTORE f22, (RISCV_FOFFSET + RISCV_FSIZE * 22)(a0) + FSTORE f23, (RISCV_FOFFSET + RISCV_FSIZE * 23)(a0) + FSTORE f24, (RISCV_FOFFSET + RISCV_FSIZE * 24)(a0) + FSTORE f25, (RISCV_FOFFSET + RISCV_FSIZE * 25)(a0) + FSTORE f26, (RISCV_FOFFSET + RISCV_FSIZE * 26)(a0) + FSTORE f27, (RISCV_FOFFSET + RISCV_FSIZE * 27)(a0) + FSTORE f28, (RISCV_FOFFSET + RISCV_FSIZE * 28)(a0) + FSTORE f29, (RISCV_FOFFSET + RISCV_FSIZE * 29)(a0) + FSTORE f30, (RISCV_FOFFSET + RISCV_FSIZE * 30)(a0) + FSTORE f31, (RISCV_FOFFSET + RISCV_FSIZE * 31)(a0) +# endif li a0, 0 // return UNW_ESUCCESS ret // jump to ra diff --git a/contrib/libs/libunwind/src/assembly.h b/contrib/libs/libunwind/src/assembly.h index 29c990a5c1..978f6bd619 100644 --- a/contrib/libs/libunwind/src/assembly.h +++ b/contrib/libs/libunwind/src/assembly.h @@ -34,35 +34,35 @@ #define PPC64_OFFS_V 824 #elif defined(__APPLE__) && defined(__aarch64__) #define SEPARATOR %% -#elif defined(__riscv) -# define RISCV_ISIZE (__riscv_xlen / 8) -# define RISCV_FOFFSET (RISCV_ISIZE * 32) -# if defined(__riscv_flen) -# define RISCV_FSIZE (__riscv_flen / 8) -# endif - -# if __riscv_xlen == 64 -# define ILOAD ld -# define ISTORE sd -# elif __riscv_xlen == 32 -# define ILOAD lw -# define ISTORE sw -# else -# error "Unsupported __riscv_xlen" -# endif - -# if defined(__riscv_flen) -# if __riscv_flen == 64 -# define FLOAD fld -# define FSTORE fsd -# elif __riscv_flen == 32 -# define FLOAD flw -# define FSTORE fsw -# else -# error "Unsupported __riscv_flen" -# endif -# endif -# define SEPARATOR ; +#elif defined(__riscv) +# define RISCV_ISIZE (__riscv_xlen / 8) +# define RISCV_FOFFSET (RISCV_ISIZE * 32) +# if defined(__riscv_flen) +# define RISCV_FSIZE (__riscv_flen / 8) +# endif + +# if __riscv_xlen == 64 +# define ILOAD ld +# define ISTORE sd +# elif __riscv_xlen == 32 +# define ILOAD lw +# define ISTORE sw +# else +# error "Unsupported __riscv_xlen" +# endif + +# if defined(__riscv_flen) +# if __riscv_flen == 64 +# define FLOAD fld +# define FSTORE fsd +# elif __riscv_flen == 32 +# define FLOAD flw +# define FSTORE fsw +# else +# error "Unsupported __riscv_flen" +# endif +# endif +# define SEPARATOR ; #else #define SEPARATOR ; #endif @@ -117,15 +117,15 @@ #if defined(__APPLE__) #define SYMBOL_IS_FUNC(name) -#define HIDDEN_SYMBOL(name) .private_extern name -#if defined(_LIBUNWIND_HIDE_SYMBOLS) -#define EXPORT_SYMBOL(name) HIDDEN_SYMBOL(name) -#else +#define HIDDEN_SYMBOL(name) .private_extern name +#if defined(_LIBUNWIND_HIDE_SYMBOLS) +#define EXPORT_SYMBOL(name) HIDDEN_SYMBOL(name) +#else #define EXPORT_SYMBOL(name) -#endif +#endif #define WEAK_ALIAS(name, aliasname) \ .globl SYMBOL_NAME(aliasname) SEPARATOR \ - EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ + EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ SYMBOL_NAME(aliasname) = SYMBOL_NAME(name) #define NO_EXEC_STACK_DIRECTIVE @@ -137,23 +137,23 @@ #else #define SYMBOL_IS_FUNC(name) .type name,@function #endif -#define HIDDEN_SYMBOL(name) .hidden name -#if defined(_LIBUNWIND_HIDE_SYMBOLS) -#define EXPORT_SYMBOL(name) HIDDEN_SYMBOL(name) -#else +#define HIDDEN_SYMBOL(name) .hidden name +#if defined(_LIBUNWIND_HIDE_SYMBOLS) +#define EXPORT_SYMBOL(name) HIDDEN_SYMBOL(name) +#else #define EXPORT_SYMBOL(name) -#endif +#endif #define WEAK_SYMBOL(name) .weak name #if defined(__hexagon__) -#define WEAK_ALIAS(name, aliasname) \ - EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ - WEAK_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ +#define WEAK_ALIAS(name, aliasname) \ + EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ + WEAK_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ .equiv SYMBOL_NAME(aliasname), SYMBOL_NAME(name) #else #define WEAK_ALIAS(name, aliasname) \ - EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ - WEAK_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ + EXPORT_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ + WEAK_SYMBOL(SYMBOL_NAME(aliasname)) SEPARATOR \ SYMBOL_NAME(aliasname) = SYMBOL_NAME(name) #endif @@ -175,7 +175,7 @@ .section .drectve,"yn" SEPARATOR \ .ascii "-export:", #name, "\0" SEPARATOR \ .text -#if defined(_LIBUNWIND_HIDE_SYMBOLS) +#if defined(_LIBUNWIND_HIDE_SYMBOLS) #define EXPORT_SYMBOL(name) #else #define EXPORT_SYMBOL(name) EXPORT_SYMBOL2(name) @@ -235,7 +235,7 @@ #endif /* __arm__ */ #if defined(__powerpc__) -#define PPC_LEFT_SHIFT(index) << (index) -#endif - +#define PPC_LEFT_SHIFT(index) << (index) +#endif + #endif /* UNWIND_ASSEMBLY_H */ diff --git a/contrib/libs/libunwind/src/config.h b/contrib/libs/libunwind/src/config.h index fa898049d9..560edda04e 100644 --- a/contrib/libs/libunwind/src/config.h +++ b/contrib/libs/libunwind/src/config.h @@ -52,8 +52,8 @@ #endif #endif -#if defined(_LIBUNWIND_HIDE_SYMBOLS) - // The CMake file passes -fvisibility=hidden to control ELF/Mach-O visibility. +#if defined(_LIBUNWIND_HIDE_SYMBOLS) + // The CMake file passes -fvisibility=hidden to control ELF/Mach-O visibility. #define _LIBUNWIND_EXPORT #define _LIBUNWIND_HIDDEN #else @@ -71,11 +71,11 @@ #define SYMBOL_NAME(name) XSTR(__USER_LABEL_PREFIX__) #name #if defined(__APPLE__) -#if defined(_LIBUNWIND_HIDE_SYMBOLS) +#if defined(_LIBUNWIND_HIDE_SYMBOLS) #define _LIBUNWIND_ALIAS_VISIBILITY(name) __asm__(".private_extern " name); -#else -#define _LIBUNWIND_ALIAS_VISIBILITY(name) -#endif +#else +#define _LIBUNWIND_ALIAS_VISIBILITY(name) +#endif #define _LIBUNWIND_WEAK_ALIAS(name, aliasname) \ __asm__(".globl " SYMBOL_NAME(aliasname)); \ __asm__(SYMBOL_NAME(aliasname) " = " SYMBOL_NAME(name)); \ diff --git a/contrib/libs/libunwind/src/libunwind.cpp b/contrib/libs/libunwind/src/libunwind.cpp index cef4f4b385..03f8b75b5b 100644 --- a/contrib/libs/libunwind/src/libunwind.cpp +++ b/contrib/libs/libunwind/src/libunwind.cpp @@ -71,10 +71,10 @@ _LIBUNWIND_HIDDEN int __unw_init_local(unw_cursor_t *cursor, #define REGISTER_KIND Registers_sparc64 #elif defined(__sparc__) # define REGISTER_KIND Registers_sparc -#elif defined(__riscv) +#elif defined(__riscv) # define REGISTER_KIND Registers_riscv -#elif defined(__ve__) -# define REGISTER_KIND Registers_ve +#elif defined(__ve__) +# define REGISTER_KIND Registers_ve #else # error Architecture not supported #endif |