Fifo VXD commit

8 files changed, 170 insertions, 28 deletions

diff --git a/control.c b/control.c
index 8c487bd..77f9b37 100644
--- a/control.c
+++ b/control.c
@@ -204,32 +204,34 @@ uint32_t FixDevCap(uint32_t cap_id, uint32_t cap_val)
 	switch(cap_id)

 	{

 		case SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:

-#ifdef CAP_R5G6B5_ALWAYS_WRONG

 		{

-			uint32_t xrgb8888 = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

-			xrgb8888 &= ~SVGA3DFORMAT_OP_SRGBWRITE; /* nvidia */

-			return xrgb8888;

-		}

-#else

-			if(cap_val & SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET) /* VirtualBox BUG */

+			if(gSVGA.userFlags & SVGA_USER_FLAGS_RGB565_BROKEN)

 			{

 				uint32_t xrgb8888 = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

 				xrgb8888 &= ~SVGA3DFORMAT_OP_SRGBWRITE; /* nvidia */

 				return xrgb8888;

 			}

-			

-			if((cap_val & SVGA3DFORMAT_OP_3DACCELERATION) == 0) /* VirtualBox BUG, older drivers */

+			else

 			{

-				uint32_t xrgb8888 = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

-				xrgb8888 &= ~SVGA3DFORMAT_OP_SRGBWRITE; /* nvidia */

-				if(xrgb8888 & SVGA3DFORMAT_OP_3DACCELERATION)

+				if(cap_val & SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET) /* VirtualBox BUG */

 				{

+					uint32_t xrgb8888 = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

+					xrgb8888 &= ~SVGA3DFORMAT_OP_SRGBWRITE; /* nvidia */

 					return xrgb8888;

 				}

+				

+				if((cap_val & SVGA3DFORMAT_OP_3DACCELERATION) == 0) /* VirtualBox BUG, older drivers */

+				{

+					uint32_t xrgb8888 = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

+					xrgb8888 &= ~SVGA3DFORMAT_OP_SRGBWRITE; /* nvidia */

+					if(xrgb8888 & SVGA3DFORMAT_OP_3DACCELERATION)

+					{

+						return xrgb8888;

+					}

+				}

 			}

-#endif

-			

-			break;

+		}

+		break;

 	}

 	

 	return cap_val;

diff --git a/control_vxd.c b/control_vxd.c
index 2c432ea..c680047 100644
--- a/control_vxd.c
+++ b/control_vxd.c
@@ -295,4 +295,61 @@ void VXD_get_addr(DWORD __far *lpLinFB, DWORD __far *lpLinFifo, DWORD __far *lpL
 	*lpLinFifoBounce = linFifoBounce;

 }

 

+void VXD_get_flags(DWORD __far *lpFlags)

+{

+	static DWORD flags = 0;

+	

+	if(VXD_srv != 0)

+	{

+		_asm

+		{

+			.386

+			push eax

+			push edx

+			

+			push ecx

+			

+		  mov edx, VMWSVXD_PM16_GET_FLAGS

+		  call dword ptr [VXD_srv]

+			

+			mov [flags], ecx

+			

+			pop ecx

+			

+			pop edx

+			pop eax

+		}

+	}

+	

+	*lpFlags = flags;

+}

 

+BOOL VXD_FIFOCommit(DWORD bytes)

+{

+	static DWORD sbytes;

+

+	sbytes = bytes;

+	

+	if(VXD_srv != 0)

+	{

+		_asm

+		{

+			.386

+			push eax

+			push edx

+			push ecx

+			

+			mov ecx, [sbytes]

+		  mov edx, VMWSVXD_PM16_FIFO_COMMIT

+		  call dword ptr [VXD_srv]

+			

+			pop ecx

+			pop edx

+			pop eax

+		}

+	

+		return TRUE;

+	}

+	

+	return FALSE;

+}

diff --git a/control_vxd.h b/control_vxd.h
index c65e0eb..9a839d6 100644
--- a/control_vxd.h
+++ b/control_vxd.h
@@ -9,5 +9,11 @@ DWORD VXD_apiver();
 void CB_start();

 void CB_stop();

 void VXD_get_addr(DWORD __far *lpLinFB, DWORD __far *lpLinFifo, DWORD __far *lpLinFifoBounce);

+void VXD_get_flags(DWORD __far *lpFlags);

+

+BOOL VXD_FIFOCommit(DWORD bytes);

+

+#define VXD_FIFOCommitAll() \

+	if(VXD_FIFOCommit(gSVGA.fifo.reservedSize)){gSVGA.fifo.reservedSize = 0;}else{SVGA_FIFOCommitAll();}

 

 #endif

diff --git a/modes.c b/modes.c
index 965a225..404631b 100644
--- a/modes.c
+++ b/modes.c
@@ -214,7 +214,7 @@ static int IsModeOK( WORD wXRes, WORD wYRes, WORD wBpp )
     

 #ifdef SVGA

     /* some implementations not support 8 and 16 bpp */

-    if(gSVGA.only32bit && wBpp != 32)

+    if((gSVGA.userFlags & SVGA_USER_FLAGS_32BITONLY) && wBpp != 32)

     {

       return 0;

     }

@@ -333,7 +333,7 @@ static void SVGA_defineScreen(unsigned wXRes, unsigned wYRes, unsigned wBpp)
     

     screen->screen.backingStore.pitch = CalcPitch(wXRes, wBpp);

     

-    SVGA_FIFOCommitAll();

+    VXD_FIFOCommitAll();

   }

   

   /* set GMR to same location as screen */

@@ -356,7 +356,7 @@ static void SVGA_defineScreen(unsigned wXRes, unsigned wYRes, unsigned wBpp)
 	  		fbgmr->format.bitsPerPixel = 16;

 	  	}

 	  }

-	  SVGA_FIFOCommitAll();

+	  VXD_FIFOCommitAll();

 	}

 }

 

@@ -371,6 +371,16 @@ static BOOL SVGA_hasAccelScreen()
   return FALSE;

 }

 

+static void VXD_Update(uint32 x, uint32 y, uint32 width, uint32 height)

+{

+	SVGAFifoCmdUpdate FARP *cmd = SVGA_FIFOReserveCmd(SVGA_CMD_UPDATE, sizeof *cmd);

+	cmd->x = x;

+	cmd->y = y;

+	cmd->width = width;

+	cmd->height = height;

+	VXD_FIFOCommitAll();

+}

+

 static DWORD SVGA_partial_update_cnt = 0;

 

 /* Update screen rect if its relevant */

@@ -386,7 +396,7 @@ extern void __loadds SVGA_UpdateRect(LONG x, LONG y, LONG w, LONG h)
   {

     if(SVGAHDA_trylock(LOCK_FIFO))

     {

-      SVGA_Update(0, 0, wScreenX, wScreenY);

+      VXD_Update(0, 0, wScreenX, wScreenY);

       SVGAHDA_unlock(LOCK_FIFO);

       SVGA_partial_update_cnt = 0;

     }

@@ -402,7 +412,7 @@ extern void __loadds SVGA_UpdateRect(LONG x, LONG y, LONG w, LONG h)
   {

     if(SVGAHDA_trylock(LOCK_FIFO))

     {

-      SVGA_Update(x, y, w, h);

+      VXD_Update(x, y, w, h);

       SVGAHDA_unlock(LOCK_FIFO);

     }

     else

@@ -436,9 +446,12 @@ static int __loadds SVGA_full_init()
     return rc;

   }

   

-  /* get system linear addressed from PM32 RING-0 driver */

+  /* get system linear addresses from PM32 RING-0 driver */

   VXD_get_addr(&gSVGA.fbLinear, &gSVGA.fifoLinear, &gSVGA.fifo.bounceLinear);

   

+  /* get user flags */

+  VXD_get_flags(&gSVGA.userFlags);

+  

   dbg_printf("VXD: received %lX %lX %lX\n",

   	gSVGA.fbLinear,

   	gSVGA.fifoLinear, 

diff --git a/vmware/svga.c b/vmware/svga.c
index 2463e8d..9a5d7bc 100644
--- a/vmware/svga.c
+++ b/vmware/svga.c
@@ -273,18 +273,16 @@ SVGA_Init(Bool enableFIFO)
    gSVGA.fifoAct    = 0;
    
 #ifdef VXD32
-   /* set if SVGA supporting different BPP then 32 */
+	gSVGA.userFlags = 0;
+
+   /* check if SVGA supporting different BPP then 32 */
    SVGA_WriteReg(SVGA_REG_ENABLE, TRUE);
    SVGA_WriteReg(SVGA_REG_CONFIG_DONE, TRUE);
    
    SVGA_WriteReg(SVGA_REG_BITS_PER_PIXEL, 8);
    if(SVGA_ReadReg(SVGA_REG_CONFIG_DONE) == 0)
    {
-      gSVGA.only32bit = 1;
-   }
-   else
-   {
-      gSVGA.only32bit = 0;
+      gSVGA.userFlags |= SVGA_USER_FLAGS_32BITONLY;
    }
    SVGA_WriteReg(SVGA_REG_ENABLE, FALSE);
    SVGA_WriteReg(SVGA_REG_CONFIG_DONE, FALSE);
diff --git a/vmware/svga.h b/vmware/svga.h
index bb2bd2b..4408007 100644
--- a/vmware/svga.h
+++ b/vmware/svga.h
@@ -92,7 +92,7 @@ typedef struct SVGADevice {
    uint16 vendorId;
    uint16 deviceId;
    /* adapter in QEMU works only on 32bit */
-   uint32 only32bit;
+   uint32 userFlags;
 
 #ifndef REALLY_TINY
    volatile struct {
@@ -108,6 +108,21 @@ typedef struct SVGADevice {
 
 #define SVGA_BOUNCE_SIZE (16*1024)
 
+/* SVGA working only on 32bpp modes */
+#define SVGA_USER_FLAGS_32BITONLY 1
+
+/* SVGA using HW cursor */
+#define SVGA_USER_FLAGS_HWCURSOR  2
+
+/* SVGA using alpha channel cursor */
+#define SVGA_USER_FLAGS_ALPHA_CUR 4
+
+/* SVGA surface 565 is broken (VBox bug) */
+#define SVGA_USER_FLAGS_RGB565_BROKEN 8
+
+/* limit SVGA VRAM to 128 MB */
+#define SVGA_USER_FLAGS_128MB_MAX 16
+
 extern SVGADevice gSVGA;
 
 #ifndef VXD32
diff --git a/vmwsvxd.c b/vmwsvxd.c
index 2958b44..41256a9 100644
--- a/vmwsvxd.c
+++ b/vmwsvxd.c
@@ -955,9 +955,46 @@ WORD __stdcall VMWS_API_Proc(PCRS_32 state)
 			rc = 1;

 			break;

 		case VMWSVXD_PM16_FIFO_COMMIT:

+		{

+			DWORD cmd_size = state->Client_ECX;

+			if(cb_support && cb_context0) /* command buffer is supported - use CB instead of FIFO */

+			{

+				SVGACBHeader *cb = (SVGACBHeader *)gSVGA.fifo.bounceLinear;

+				memset(cb, 0, sizeof(SVGACBHeader));

+

+				cb->length     = cmd_size;

+				cb->status     = SVGA_CB_STATUS_NONE;

+				cb->ptr.pa.hi  = 0;

+				cb->ptr.pa.low = gSVGA.fifo.bouncePhy + PAGE_SIZE;

+				cb->flags      = SVGA_CB_FLAG_NO_IRQ;

+				

+				cb->id.low     = cmd_buf_next_id.low;

+				cb->id.hi      = cmd_buf_next_id.hi;

+				

+				SVGA_WriteReg(SVGA_REG_COMMAND_HIGH, 0);

+				SVGA_WriteReg(SVGA_REG_COMMAND_LOW, gSVGA.fifo.bouncePhy | SVGA_CB_CONTEXT_0);

+				

+				nextID_CB();

+				

+				/* wait to complete */

+				while(cb->status == SVGA_CB_STATUS_NONE)

+				{

+					SVGA_WriteReg(SVGA_REG_SYNC, 1);

+				}

+			}

+			else /* use FIFO */

+			{

+				gSVGA.fifo.reservedSize = cmd_size;

+				SVGA_FIFOCommit(cmd_size);

+			}

 			

 			rc = 1;

 			break;

+		}

+		case VMWSVXD_PM16_GET_FLAGS:

+			state->Client_ECX = gSVGA.userFlags;

+			break;

+		

 	}

 	

 	if(rc == 0xFFFF)

@@ -1009,6 +1046,19 @@ void Device_Init_proc()
 	

 	if(SVGA_Init(FALSE) == 0)

 	{

+		/* default flags */

+		gSVGA.userFlags |= SVGA_USER_FLAGS_RGB565_BROKEN | SVGA_USER_FLAGS_128MB_MAX;

+		

+		// TODO: read config from registry

+		

+		if(gSVGA.userFlags & SVGA_USER_FLAGS_128MB_MAX)

+		{

+			if(gSVGA.vramSize > 128*1024*1024)

+			{

+				gSVGA.vramSize = 128*1024*1024;

+			}

+		}

+		

 		dbg_printf(dbg_Device_Init_proc_succ);

 		svga_init_success = TRUE;

 		

diff --git a/vmwsvxd.h b/vmwsvxd.h
index 0941fcc..da37569 100644
--- a/vmwsvxd.h
+++ b/vmwsvxd.h
@@ -20,5 +20,6 @@
 #define VMWSVXD_PM16_CB_STOP                      9

 #define VMWSVXD_PM16_GET_ADDR                     10

 #define VMWSVXD_PM16_FIFO_COMMIT                  11

+#define VMWSVXD_PM16_GET_FLAGS                    12

 

 #endif