rendering optimalization

5 files changed, 355 insertions, 22 deletions

diff --git a/control.c b/control.c
index 40a996f..8c487bd 100644
--- a/control.c
+++ b/control.c
@@ -293,11 +293,20 @@ WORD SVGA_3DSupport()
 	{

 		if(GetDevCap(SVGA3D_DEVCAP_3D)) /* is 3D enabled */

 		{

-			uint32_t surfcap = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

-			if((surfcap & SVGA3DFORMAT_OP_3DACCELERATION) != 0) /* at last X8R8G8B8 needs to be accelerated! */

+			uint32_t cap_xgrb = GetDevCap(SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8);

+			uint32_t cap_dx_xgrb = GetDevCap(SVGA3D_DEVCAP_DXFMT_X8R8G8B8);

+			if((cap_xgrb & SVGA3DFORMAT_OP_3DACCELERATION) != 0) /* at last X8R8G8B8 needs to be accelerated! */

 			{

 				return 1;

 			}

+			else if((cap_dx_xgrb & SVGA3DFORMAT_OP_TEXTURE) != 0) /* vGPU10 - DX11 mode */

+			{

+				return 1;

+			}

+			else

+			{

+				dbg_printf("no surface caps %lX %lX!\n", cap_xgrb, cap_dx_xgrb);

+			}

 		}

 		else

 		{

@@ -312,6 +321,8 @@ WORD SVGA_3DSupport()
 	return 0;

 }

 

+#define SVGA3D_MAX_MOBS 33280UL /* SVGA3D_MAX_CONTEXT_IDS + SVGA3D_MAX_CONTEXT_IDS + SVGA3D_MAX_SURFACE_IDS */

+

 /**

  * init SVGAHDA -> memory map between user space and (virtual) hardware memory

  *

@@ -324,6 +335,7 @@ void SVGAHDA_init()
   SVGAHDA.ul_fence_index = SVGAHDA.ul_flags_index + 8;

   SVGAHDA.ul_gmr_start   = SVGAHDA.ul_fence_index + 1;

   SVGAHDA.ul_gmr_count   = SVGA_ReadReg(SVGA_REG_GMR_MAX_IDS);

+  //SVGAHDA.ul_gmr_count   = SVGA3D_MAX_MOBS;

   SVGAHDA.ul_ctx_start   = SVGAHDA.ul_gmr_start + SVGAHDA.ul_gmr_count*GMR_INDEX_CNT;

   SVGAHDA.ul_ctx_count   = GetDevCap(SVGA3D_DEVCAP_MAX_CONTEXT_IDS);

   SVGAHDA.ul_surf_start  = SVGAHDA.ul_ctx_start + SVGAHDA.ul_ctx_count*CTX_INDEX_CNT;

@@ -343,7 +355,7 @@ void SVGAHDA_init()
 		SVGAHDA.userlist_pm16[ULF_LOCK_FIFO] = 0;

 	}

 	

-	dbg_printf("SVGAHDA_init\n");

+	dbg_printf("SVGAHDA_init: %ld\n", SVGAHDA.userlist_length * sizeof(uint32_t));

 }

 

 /**

@@ -514,7 +526,7 @@ LONG WINAPI __loadds Control(LPVOID lpDevice, UINT function,
 {

 	LONG rc = -1;

 	

-	dbg_printf("Control (16bit): %d (0x%x)\n", function, function);

+	//dbg_printf("Control (16bit): %d (0x%x)\n", function, function);

 	

   if(function == QUERYESCSUPPORT)

   {

diff --git a/modes.c b/modes.c
index 2a7e8fd..fd56fbf 100644
--- a/modes.c
+++ b/modes.c
@@ -310,6 +310,7 @@ static DWORD AllocLinearSelector(DWORD dwPhysAddr, DWORD dwSize, DWORD __far * l
 static void SVGA_defineScreen(unsigned wXRes, unsigned wYRes, unsigned wBpp)

 {

   SVGAFifoCmdDefineScreen __far *screen;

+  SVGAFifoCmdDefineGMRFB __far *fbgmr;

    

   /* create screen 0 */

   screen = SVGA_FIFOReserveCmd(SVGA_CMD_DEFINE_SCREEN, sizeof(SVGAFifoCmdDefineScreen));

@@ -330,6 +331,29 @@ static void SVGA_defineScreen(unsigned wXRes, unsigned wYRes, unsigned wBpp)
     

     SVGA_FIFOCommitAll();

   }

+  

+  /* set GMR to same location as screen */

+  if(wBpp >= 15)

+  {

+	  fbgmr = SVGA_FIFOReserveCmd(SVGA_CMD_DEFINE_GMRFB, sizeof(SVGAFifoCmdDefineGMRFB));

+	  

+	  if(fbgmr)

+	  {

+	  	fbgmr->ptr.gmrId = SVGA_GMR_FRAMEBUFFER;

+	  	fbgmr->ptr.offset = 0;

+	  	fbgmr->bytesPerLine = CalcPitch(wXRes, wBpp);

+	  	fbgmr->format.colorDepth = wBpp;

+	  	if(wBpp >= 24)

+	  	{

+	  		fbgmr->format.bitsPerPixel = 32;

+	  	}

+	  	else

+	  	{

+	  		fbgmr->format.bitsPerPixel = 16;

+	  	}

+	  }

+	  SVGA_FIFOCommitAll();

+	}

 }

 

 /* Check if screen acceleration is available */

@@ -460,6 +484,7 @@ static int SetDisplayMode( WORD wXRes, WORD wYRes, int bFullSet )
       CB_stop();

       

       SVGA_SetMode(wXRes, wYRes, wBpp); /* setup by legacy registry */

+      SVGA_Flush(); /* make sure, that is really set */

       wMesa3DEnabled = 0;

       if(SVGA3D_Init())

       {

diff --git a/version.h b/version.h
index 596dab6..b625f5d 100644
--- a/version.h
+++ b/version.h
@@ -5,7 +5,7 @@
 #define DRV_STR(x) DRV_STR_(x)

 

 /* DRV, VXD and DLL have to have the same */

-#define DRV_API_LEVEL 20230807UL

+#define DRV_API_LEVEL 20230814UL

 

 /* on binaries equals 1 and for INF is 1 = separate driver, 2 = softgpu pack */

 #define DRV_VER_MAJOR 1

diff --git a/vmware/svga3d_reg.h b/vmware/svga3d_reg.h
index e9f7703..3bcb4ae 100644
--- a/vmware/svga3d_reg.h
+++ b/vmware/svga3d_reg.h
@@ -2269,11 +2269,254 @@ typedef enum {
    SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM              = 83,
 
    /*
-    * Don't add new caps into the previous section; the values in this
-    * enumeration must not change. You can put new values right before
-    * SVGA3D_DEVCAP_MAX.
+    * Deprecated.
     */
-   SVGA3D_DEVCAP_MAX                                  /* This must be the last index. */
+   SVGA3D_DEVCAP_DEAD1                             = 84,
+   SVGA3D_DEVCAP_DEAD8                             = 85,
+   SVGA3D_DEVCAP_DEAD9                             = 86,
+
+   SVGA3D_DEVCAP_LINE_AA                           = 87,  /* boolean */
+   SVGA3D_DEVCAP_LINE_STIPPLE                      = 88,  /* boolean */
+   SVGA3D_DEVCAP_MAX_LINE_WIDTH                    = 89,  /* float */
+   SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH                 = 90,  /* float */
+
+   SVGA3D_DEVCAP_SURFACEFMT_YV12                   = 91,
+
+   /*
+    * Deprecated.
+    */
+   SVGA3D_DEVCAP_DEAD3                             = 92,
+
+   /*
+    * Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
+    */
+   SVGA3D_DEVCAP_TS_COLOR_KEY                      = 93, /* boolean */
+
+   /*
+    * Deprecated.
+    */
+   SVGA3D_DEVCAP_DEAD2                             = 94,
+
+   /*
+    * Does the device support DXContexts?  (ie DX10 era rendering)
+    */
+   SVGA3D_DEVCAP_DXCONTEXT                         = 95,
+
+   /*
+    * What is the maximum size of a texture array?
+    *
+    * (Even if this cap is zero, cubemaps are still allowed.)
+    */
+   SVGA3D_DEVCAP_MAX_TEXTURE_ARRAY_SIZE            = 96,
+
+   /*
+    * What is the maximum number of vertex buffers or vertex input registers
+    * that can be expected to work correctly with a DXContext?
+    *
+    * The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
+    * anything in excess of this cap is not guaranteed to render correctly.
+    *
+    * Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
+    * input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
+    * SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
+    * but only the registers up to this cap value are guaranteed to render
+    * correctly.
+    *
+    * If guest-drivers are able to expose a lower-limit, it's recommended
+    * that they clamp to this value.  Otherwise, the host will make a
+    * best-effort on case-by-case basis if guests exceed this.
+    */
+   SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS              = 97,
+
+   /*
+    * What is the maximum number of constant buffers that can be expected to
+    * work correctly with a DX context?
+    *
+    * The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
+    * anything in excess of this cap is not guaranteed to render correctly.
+    *
+    * If guest-drivers are able to expose a lower-limit, it's recommended
+    * that they clamp to this value.  Otherwise, the host will make a
+    * best-effort on case-by-case basis if guests exceed this.
+    */
+   SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS           = 98,
+
+   /*
+    * Does the device support provoking vertex control?
+    *
+    * If this cap is present, the provokingVertexLast field in the
+    * rasterizer state is enabled.  (Guests can then set it to FALSE,
+    * meaning that the first vertex is the provoking vertex, or TRUE,
+    * meaning that the last vertex is the provoking vertex.)
+    *
+    * If this cap is FALSE, then guests should set the provokingVertexLast
+    * to FALSE, otherwise rendering behavior is undefined.
+    */
+   SVGA3D_DEVCAP_DX_PROVOKING_VERTEX               = 99,
+
+   SVGA3D_DEVCAP_DXFMT_X8R8G8B8                    = 100,
+   SVGA3D_DEVCAP_DXFMT_A8R8G8B8                    = 101,
+   SVGA3D_DEVCAP_DXFMT_R5G6B5                      = 102,
+   SVGA3D_DEVCAP_DXFMT_X1R5G5B5                    = 103,
+   SVGA3D_DEVCAP_DXFMT_A1R5G5B5                    = 104,
+   SVGA3D_DEVCAP_DXFMT_A4R4G4B4                    = 105,
+   SVGA3D_DEVCAP_DXFMT_Z_D32                       = 106,
+   SVGA3D_DEVCAP_DXFMT_Z_D16                       = 107,
+   SVGA3D_DEVCAP_DXFMT_Z_D24S8                     = 108,
+   SVGA3D_DEVCAP_DXFMT_Z_D15S1                     = 109,
+   SVGA3D_DEVCAP_DXFMT_LUMINANCE8                  = 110,
+   SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4           = 111,
+   SVGA3D_DEVCAP_DXFMT_LUMINANCE16                 = 112,
+   SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8           = 113,
+   SVGA3D_DEVCAP_DXFMT_DXT1                        = 114,
+   SVGA3D_DEVCAP_DXFMT_DXT2                        = 115,
+   SVGA3D_DEVCAP_DXFMT_DXT3                        = 116,
+   SVGA3D_DEVCAP_DXFMT_DXT4                        = 117,
+   SVGA3D_DEVCAP_DXFMT_DXT5                        = 118,
+   SVGA3D_DEVCAP_DXFMT_BUMPU8V8                    = 119,
+   SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5                  = 120,
+   SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8                = 121,
+   SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1                = 122,
+   SVGA3D_DEVCAP_DXFMT_ARGB_S10E5                  = 123,
+   SVGA3D_DEVCAP_DXFMT_ARGB_S23E8                  = 124,
+   SVGA3D_DEVCAP_DXFMT_A2R10G10B10                 = 125,
+   SVGA3D_DEVCAP_DXFMT_V8U8                        = 126,
+   SVGA3D_DEVCAP_DXFMT_Q8W8V8U8                    = 127,
+   SVGA3D_DEVCAP_DXFMT_CxV8U8                      = 128,
+   SVGA3D_DEVCAP_DXFMT_X8L8V8U8                    = 129,
+   SVGA3D_DEVCAP_DXFMT_A2W10V10U10                 = 130,
+   SVGA3D_DEVCAP_DXFMT_ALPHA8                      = 131,
+   SVGA3D_DEVCAP_DXFMT_R_S10E5                     = 132,
+   SVGA3D_DEVCAP_DXFMT_R_S23E8                     = 133,
+   SVGA3D_DEVCAP_DXFMT_RG_S10E5                    = 134,
+   SVGA3D_DEVCAP_DXFMT_RG_S23E8                    = 135,
+   SVGA3D_DEVCAP_DXFMT_BUFFER                      = 136,
+   SVGA3D_DEVCAP_DXFMT_Z_D24X8                     = 137,
+   SVGA3D_DEVCAP_DXFMT_V16U16                      = 138,
+   SVGA3D_DEVCAP_DXFMT_G16R16                      = 139,
+   SVGA3D_DEVCAP_DXFMT_A16B16G16R16                = 140,
+   SVGA3D_DEVCAP_DXFMT_UYVY                        = 141,
+   SVGA3D_DEVCAP_DXFMT_YUY2                        = 142,
+   SVGA3D_DEVCAP_DXFMT_NV12                        = 143,
+   SVGA3D_DEVCAP_FORMAT_DEAD2                       = 144,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS       = 145,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT           = 146,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT           = 147,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS          = 148,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT             = 149,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT              = 150,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT              = 151,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS       = 152,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT           = 153,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM          = 154,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT           = 155,
+   SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS             = 156,
+   SVGA3D_DEVCAP_DXFMT_R32G32_UINT                 = 157,
+   SVGA3D_DEVCAP_DXFMT_R32G32_SINT                 = 158,
+   SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS           = 159,
+   SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT        = 160,
+   SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24             = 161,
+   SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT              = 162,
+   SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS        = 163,
+   SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT            = 164,
+   SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT             = 165,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS           = 166,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM              = 167,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB         = 168,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT               = 169,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT               = 170,
+   SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS             = 171,
+   SVGA3D_DEVCAP_DXFMT_R16G16_UINT                 = 172,
+   SVGA3D_DEVCAP_DXFMT_R16G16_SINT                 = 173,
+   SVGA3D_DEVCAP_DXFMT_R32_TYPELESS                = 174,
+   SVGA3D_DEVCAP_DXFMT_D32_FLOAT                   = 175,
+   SVGA3D_DEVCAP_DXFMT_R32_UINT                    = 176,
+   SVGA3D_DEVCAP_DXFMT_R32_SINT                    = 177,
+   SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS              = 178,
+   SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT           = 179,
+   SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8                = 180,
+   SVGA3D_DEVCAP_DXFMT_X24_G8_UINT                 = 181,
+   SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS               = 182,
+   SVGA3D_DEVCAP_DXFMT_R8G8_UNORM                  = 183,
+   SVGA3D_DEVCAP_DXFMT_R8G8_UINT                   = 184,
+   SVGA3D_DEVCAP_DXFMT_R8G8_SINT                   = 185,
+   SVGA3D_DEVCAP_DXFMT_R16_TYPELESS                = 186,
+   SVGA3D_DEVCAP_DXFMT_R16_UNORM                   = 187,
+   SVGA3D_DEVCAP_DXFMT_R16_UINT                    = 188,
+   SVGA3D_DEVCAP_DXFMT_R16_SNORM                   = 189,
+   SVGA3D_DEVCAP_DXFMT_R16_SINT                    = 190,
+   SVGA3D_DEVCAP_DXFMT_R8_TYPELESS                 = 191,
+   SVGA3D_DEVCAP_DXFMT_R8_UNORM                    = 192,
+   SVGA3D_DEVCAP_DXFMT_R8_UINT                     = 193,
+   SVGA3D_DEVCAP_DXFMT_R8_SNORM                    = 194,
+   SVGA3D_DEVCAP_DXFMT_R8_SINT                     = 195,
+   SVGA3D_DEVCAP_DXFMT_P8                          = 196,
+   SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP          = 197,
+   SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM             = 198,
+   SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM             = 199,
+   SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS                = 200,
+   SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB              = 201,
+   SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS                = 202,
+   SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB              = 203,
+   SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS                = 204,
+   SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB              = 205,
+   SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS                = 206,
+   SVGA3D_DEVCAP_DXFMT_ATI1                        = 207,
+   SVGA3D_DEVCAP_DXFMT_BC4_SNORM                   = 208,
+   SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS                = 209,
+   SVGA3D_DEVCAP_DXFMT_ATI2                        = 210,
+   SVGA3D_DEVCAP_DXFMT_BC5_SNORM                   = 211,
+   SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM  = 212,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS           = 213,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB         = 214,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS           = 215,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB         = 216,
+   SVGA3D_DEVCAP_DXFMT_Z_DF16                      = 217,
+   SVGA3D_DEVCAP_DXFMT_Z_DF24                      = 218,
+   SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT                 = 219,
+   SVGA3D_DEVCAP_DXFMT_YV12                        = 220,
+   SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT          = 221,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT          = 222,
+   SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM          = 223,
+   SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT                = 224,
+   SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM           = 225,
+   SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM              = 226,
+   SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT                = 227,
+   SVGA3D_DEVCAP_DXFMT_R16G16_UNORM                = 228,
+   SVGA3D_DEVCAP_DXFMT_R16G16_SNORM                = 229,
+   SVGA3D_DEVCAP_DXFMT_R32_FLOAT                   = 230,
+   SVGA3D_DEVCAP_DXFMT_R8G8_SNORM                  = 231,
+   SVGA3D_DEVCAP_DXFMT_R16_FLOAT                   = 232,
+   SVGA3D_DEVCAP_DXFMT_D16_UNORM                   = 233,
+   SVGA3D_DEVCAP_DXFMT_A8_UNORM                    = 234,
+   SVGA3D_DEVCAP_DXFMT_BC1_UNORM                   = 235,
+   SVGA3D_DEVCAP_DXFMT_BC2_UNORM                   = 236,
+   SVGA3D_DEVCAP_DXFMT_BC3_UNORM                   = 237,
+   SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM                = 238,
+   SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM              = 239,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM              = 240,
+   SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM              = 241,
+   SVGA3D_DEVCAP_DXFMT_BC4_UNORM                   = 242,
+   SVGA3D_DEVCAP_DXFMT_BC5_UNORM                   = 243,
+ 
+   SVGA3D_DEVCAP_SM41                              = 244,
+   SVGA3D_DEVCAP_MULTISAMPLE_2X                    = 245,
+   SVGA3D_DEVCAP_MULTISAMPLE_4X                    = 246,
+   SVGA3D_DEVCAP_MS_FULL_QUALITY                   = 247,
+   SVGA3D_DEVCAP_LOGICOPS                          = 248,
+   SVGA3D_DEVCAP_LOGIC_BLENDOPS                    = 249,
+   SVGA3D_DEVCAP_DXFMT_B4G4R4A4_UNORM              = 250,
+   SVGA3D_DEVCAP_DXFMT_BC6H_UF16                   = 252,
+   SVGA3D_DEVCAP_DXFMT_BC6H_SF16                   = 253,
+   SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS                = 254,
+   SVGA3D_DEVCAP_DXFMT_BC7_UNORM                   = 255,
+   SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB              = 256,
+   SVGA3D_DEVCAP_DXFMT_AYUV                        = 257,
+   SVGA3D_DEVCAP_SM5                               = 258,
+   SVGA3D_DEVCAP_MULTISAMPLE_8X                    = 259,
+   SVGA3D_DEVCAP_FORCED_SAMPLE_COUNT_1             = 260,
+   SVGA3D_DEVCAP_MAX                               = 261,
+  
 } SVGA3dDevCapIndex;
 
 typedef union {
diff --git a/vmwsvxd.c b/vmwsvxd.c
index 3a88ba8..54fe7d3 100644
--- a/vmwsvxd.c
+++ b/vmwsvxd.c
@@ -143,12 +143,14 @@ typedef struct _cmd_buf_t
 #define CB_STATUS_LOCKED  1 /* buffer is using by Ring-3 proccess */

 #define CB_STATUS_PROCESS 2 /* buffer is register by VGPU */

 

-#define CB_COUNT 2

+#define CB_COUNT 4

 

 uint64 cmd_buf_next_id = {0, 0};

 

 cmd_buf_t cmd_bufs[CB_COUNT] = {{0}};

 

+int queued_cmd_buf = -1;

+

 BOOL cb_support = FALSE;

 BOOL gb_support = FALSE;

 BOOL cb_context0 = FALSE;

@@ -156,6 +158,7 @@ BOOL cb_context0 = FALSE;
 #define ROUND_TO_PAGES(_cb)((((_cb) + PAGE_SIZE - 1)/PAGE_SIZE)*PAGE_SIZE)

 

 #define SVGA3D_MAX_MOBS (SVGA3D_MAX_CONTEXT_IDS + SVGA3D_MAX_CONTEXT_IDS + SVGA3D_MAX_SURFACE_IDS)

+#define VBOX_VIDEO_MAX_SCREENS 64

 

 #define FLAG_ALLOCATED 1

 #define FLAG_ACTIVE    2

@@ -165,7 +168,7 @@ otinfo_entry_t otable[SVGA_OTABLE_DX_MAX] = {
 	{0, NULL, ROUND_TO_PAGES(SVGA3D_MAX_SURFACE_IDS*sizeof(SVGAOTableSurfaceEntry)),   0}, /* SVGA_OTABLE_SURFACE */

 	{0, NULL, ROUND_TO_PAGES(SVGA3D_MAX_CONTEXT_IDS*sizeof(SVGAOTableContextEntry)),   0}, /* SVGA_OTABLE_CONTEXT */

 	{0, NULL, 0,                                                                       0}, /* SVGA_OTABLE_SHADER - not used */

-	{0, NULL, ROUND_TO_PAGES(64*sizeof(SVGAOTableScreenTargetEntry)),                  0}, /* SVGA_OTABLE_SCREENTARGET (VBOX_VIDEO_MAX_SCREENS) */

+	{0, NULL, ROUND_TO_PAGES(VBOX_VIDEO_MAX_SCREENS*sizeof(SVGAOTableScreenTargetEntry)), 0}, /* SVGA_OTABLE_SCREENTARGET (VBOX_VIDEO_MAX_SCREENS) */

 	{0, NULL, ROUND_TO_PAGES(SVGA3D_MAX_CONTEXT_IDS*sizeof(SVGAOTableDXContextEntry)), 0}, /* SVGA_OTABLE_DXCONTEXT */

 };

 

@@ -252,6 +255,7 @@ void Sys_Critical_Init_proc()
 #define SVGA_CB_LOCK         0x1204

 #define SVGA_CB_SUBMIT       0x1205

 #define SVGA_CB_SYNC         0x1206

+#define SVGA_CB_SUBMIT_SYNC  0x1207

 

 DWORD __stdcall Device_IO_Control_entry(struct DIOCParams *params);

 

@@ -391,8 +395,7 @@ static BOOL GMRAlloc(ULONG nPages, ULONG *outDataAddr, ULONG *outGMRAddr, ULONG
 		ULONG blocks = 1;

 		ULONG blk_pages = 0;

 		

-		//laddr = _PageAllocate(nPages, PG_SYS, 0, 0, 0x0, 0x100000, NULL, PAGEFIXED);

-		laddr = 0;

+		laddr = _PageAllocate(nPages, PG_SYS, 0, 0, 0x0, 0x100000, NULL, PAGEFIXED);

 		

 		if(laddr)

 		{

@@ -636,6 +639,12 @@ static void *LockCB()
 			}

 #endif

 			cmd_bufs[index].status = CB_STATUS_LOCKED;

+			

+			if(queued_cmd_buf == index)

+			{

+				queued_cmd_buf = -1;

+			}

+			

 			return cmd_bufs[index].lin;

 		}

 	}

@@ -649,7 +658,7 @@ static void *LockCB()
  * cbctx_id = SVGA_CB_CONTEXT_0,...

  **/

 

-static BOOL submitCB(void *ptr, DWORD cbctx_id)

+static BOOL submitCB(void *ptr, DWORD cbctx_id, BOOL sync)

 {

 	int index;

 	

@@ -673,10 +682,36 @@ static BOOL submitCB(void *ptr, DWORD cbctx_id)
 				cb->id.low = cmd_buf_next_id.low;

 				cb->id.hi  = cmd_buf_next_id.hi;

 				

+#if 0

+				if(queued_cmd_buf >= 0)

+				{

+					/* wait to complete the last command */

+					SVGACBHeader *cb_queued = (SVGACBHeader *)cmd_bufs[queued_cmd_buf].lin;

+					

+					while(cb_queued->status == SVGA_CB_STATUS_NONE)

+					{

+						SVGA_WriteReg(SVGA_REG_SYNC, 1);

+					}

+				}

+#endif

+				

 				SVGA_WriteReg(SVGA_REG_COMMAND_HIGH, 0); // high part of 64-bit memory address...

 				SVGA_WriteReg(SVGA_REG_COMMAND_LOW, cmd_bufs[index].phy | cbctx_id);

 				cmd_bufs[index].status = CB_STATUS_PROCESS;

 				

+				if(sync)

+				{

+					while(cb->status == SVGA_CB_STATUS_NONE)

+					{

+						SVGA_WriteReg(SVGA_REG_SYNC, 1);

+					}

+					queued_cmd_buf = -1;

+				}

+				else

+				{

+					queued_cmd_buf = index;

+				}

+				

 				//dbg_printf(dbg_submitcb, cbctx_id);

 				

 				nextID_CB();

@@ -884,8 +919,7 @@ WORD __stdcall VMWS_API_Proc(PCRS_32 state)
 				cbe->cmd = SVGA_DC_CMD_START_STOP_CONTEXT;

 				cbe->cbstart.enable  = 1;

 				cbe->cbstart.context = SVGA_CB_CONTEXT_0;

-				submitCB(cbe, SVGA_CB_CONTEXT_DEVICE);

-				syncCB();

+				submitCB(cbe, SVGA_CB_CONTEXT_DEVICE, TRUE);

 

 				dbg_printf(dbg_cb_ena);

 				cb_context0 = TRUE;

@@ -908,7 +942,7 @@ WORD __stdcall VMWS_API_Proc(PCRS_32 state)
 				cbe->cmd = SVGA_DC_CMD_START_STOP_CONTEXT;

 				cbe->cbstart.enable  = 0;

 				cbe->cbstart.context = SVGA_CB_CONTEXT_0;

-				submitCB(cbe, SVGA_CB_CONTEXT_DEVICE);

+				submitCB(cbe, SVGA_CB_CONTEXT_DEVICE, FALSE); // FALSE?

 			}

 			rc = 1;

 			break;

@@ -1095,7 +1129,20 @@ DWORD __stdcall Device_IO_Control_entry(struct DIOCParams *params)
 			{

 				DWORD *in = (DWORD*)params->lpInBuffer;

 				

-				if(submitCB((void*)in[0], in[1]))

+				if(submitCB((void*)in[0], in[1], FALSE))

+				{

+					return 0;

+				}

+			}

+			return 1;

+		}

+		case SVGA_CB_SUBMIT_SYNC:

+		{

+			if(cb_support)

+			{

+				DWORD *in = (DWORD*)params->lpInBuffer;

+				

+				if(submitCB((void*)in[0], in[1], TRUE))

 				{

 					return 0;

 				}

@@ -1129,16 +1176,22 @@ DWORD __stdcall Device_IO_Control_entry(struct DIOCParams *params)
   		DWORD *lpOut = (DWORD*)params->lpOutBuffer;

   		DWORD gmrPPN = 0;

   		

-  		dbg_printf(dbg_region_info_1, lpIn[0]);

+  		//dbg_printf(dbg_region_info_1, lpIn[0]);

   		

 			if(GMRAlloc(lpIn[1], &lpOut[1], &lpOut[2], &gmrPPN, &lpOut[3], &lpOut[4]))

 			{

 				if(lpIn[0] != 0)

 				{

-		    	SVGA_WriteReg(SVGA_REG_GMR_ID, lpIn[0]);

-		    	SVGA_WriteReg(SVGA_REG_GMR_DESCRIPTOR, gmrPPN);

+					DWORD gmr_max = SVGA_ReadReg(SVGA_REG_GMR_MAX_IDS);

+					

+					/* if region id extends GRM max, don't register region and only use it as MOB */

+					if(lpIn[0] < gmr_max)

+					{

+		    		SVGA_WriteReg(SVGA_REG_GMR_ID, lpIn[0]);

+		    		SVGA_WriteReg(SVGA_REG_GMR_DESCRIPTOR, gmrPPN);

+		    	}

 		    	

-		    	dbg_printf(dbg_region_info_2, lpOut[1], gmrPPN, lpOut[2]);

+		    	//dbg_printf(dbg_region_info_2, lpOut[1], gmrPPN, lpOut[2]);

 		    	

 		    	/* refresh all register, so make sure that new commands will accepts this region */

 		    	SVGA_Flush();