diff options
author | Jaroslav Hensl <jara@hensl.cz> | 2025-07-29 16:42:13 +0200 |
---|---|---|
committer | Jaroslav Hensl <jara@hensl.cz> | 2025-07-29 16:42:13 +0200 |
commit | 739eb72235cba62334f8b42448c9e9c87e7d2dd6 (patch) | |
tree | 993662b164b82604215c1964188e9aeb35eb9d78 | |
parent | 12c37ec3ba15126468fb5b275d49ba8328b93a9f (diff) | |
download | vmdisp9x-main.tar.gz |
double buffering (inc. README) + version fixHEADv1.2025.0.119main
-rw-r--r-- | README.md | 17 | ||||
-rw-r--r-- | makefile | 2 | ||||
-rw-r--r-- | tools/copyinf.c | 2 | ||||
-rw-r--r-- | vmdisp9x.inf | 2 | ||||
-rw-r--r-- | vxd_vesa.c | 30 |
5 files changed, 48 insertions, 5 deletions
@@ -108,6 +108,23 @@ REGEDIT4 To test that you Video BIOS can handle this, simply run (START -> run) `command.com` and when your screen will broke (you will see full black, or some random chars) this setting is not for you. (You can press Alt+Enter to switch DOS to fullscreen and again Alt+Enter to back to window = this probably can you return to right screen mode).
+### Double buffering
+
+Most VESA card support double buffering (e.g. seamless move frame buffer to different location in VRAM). But sometime (or for some applications) this don’t work correctly and [tearing](https://wiki.osdev.org/Double_Buffering#Tearing) is too high - mostly because application control buffer flipping, but due emulation of most drawing and timing function simply doesn't catch right time. For this situation you can force double buffer emulation by this registry key:
+
+```
+REGEDIT4
+
+[HKEY_LOCAL_MACHINE\Software\vmdisp9x\vesa]
+"HWDoubleBuffer"=dword:00000000
+
+```
+
+(Default value is 2)
+
+Also note, that software double buffering can by very slow (because needs reading from video ram).
+
+
### Minimal configuration
Minimal configuration (for Windows 95 build) is Intel 486 with 16 MB ram + PCI S3 (Trio or Virge) with 4 MB VRAM. On this configuration isn't 3D available (for obvious reason). For 3D acceleration you need at last Pentium 3 CPU + 256 MB RAM. But software 3D acceleration is CPU heavy, so doesn't make any sense to run VMDisp9x on these configurations. Minimal usable configuration is around Intel Core 2 CPU with Intel 965 integrated GPU.
@@ -14,7 +14,7 @@ OBJS += & INCS = -I$(%WATCOM)\h\win -Iddk -Ivmware
-VER_BUILD = 118
+VER_BUILD = 119
FLAGS = -DDRV_VER_BUILD=$(VER_BUILD)
diff --git a/tools/copyinf.c b/tools/copyinf.c index 0dfb125..828ff3a 100644 --- a/tools/copyinf.c +++ b/tools/copyinf.c @@ -171,7 +171,7 @@ int main(int argc, char **argv) {
if(strstr(linebuf, "DriverVer=") == linebuf)
{
- sprintf(linebuf, "DriverVer=%02d/%02d/%04d, %d.%d.0.%d", month, day, year, softgpu+1, year, build);
+ sprintf(linebuf, "DriverVer=%02d/%02d/%04d,%d.%d.%d.%d", month, day, year, 4, year, softgpu, build);
}
else
{
diff --git a/vmdisp9x.inf b/vmdisp9x.inf index 013c8f1..caacecd 100644 --- a/vmdisp9x.inf +++ b/vmdisp9x.inf @@ -8,7 +8,7 @@ ; 2023-2025, Jaroslav Hensl
[version]
-DriverVer=01/01/2025, 4.2025.0.0
+DriverVer=01/01/2025,4.2025.0.0
Class=DISPLAY
signature="$CHICAGO$"
Provider=%Mfg%
@@ -125,7 +125,7 @@ static int vesa_pal_bits = 6; static BOOL vesa_valid = FALSE;
static DWORD conf_dos_window = 0;
-static DWORD conf_hw_double_buf = 0;
+static DWORD conf_hw_double_buf = 2;
#define SCREEN_EMULATED_CENTER 0
#define SCREEN_EMULATED_COPY 1
@@ -609,6 +609,8 @@ DWORD FBHDA_palette_get(unsigned char index) return 0;
}
+#define SWAP_TESTS 1024
+
BOOL FBHDA_swap(DWORD offset)
{
if((offset + hda->stride) < hda->vram_size && offset >= hda->system_surface)
@@ -639,8 +641,32 @@ BOOL FBHDA_swap(DWORD offset) (screen_mode == SCREEN_FLIP_VSYNC) ? VESA_DISPLAYSTART_VTRACE : VESA_DISPLAYSTART_SET;
regs.Client_ECX = off_x;
regs.Client_EDX = off_y;
- hda->surface = offset;
+
vesa_bios(®s);
+ if(VESA_SUCC(regs))
+ {
+ /* wait until is set */
+ DWORD test_off_x, test_off_y;
+ DWORD nums_test = 0;
+ do
+ {
+ regs.Client_EAX = VESA_CMD_DISPLAY_START;
+ regs.Client_EBX = VESA_DISPLAYSTART_GET;
+ regs.Client_ECX = 0;
+ regs.Client_EDX = 0;
+ if(!VESA_SUCC(regs))
+ {
+ break;
+ }
+ if(++nums_test > SWAP_TESTS)
+ {
+ break;
+ }
+ test_off_x = regs.Client_ECX & 0xFFFF;
+ test_off_y = regs.Client_EDX & 0xFFFF;
+ } while((test_off_x != off_x) || (test_off_y != off_y));
+ }
+ hda->surface = offset;
if(fb_lock_cnt == 0)
{
|