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authorHenrik Gramner <hengar-6@student.ltu.se>2012-04-04 20:03:15 +0000
committerJustin Ruggles <justin.ruggles@gmail.com>2012-04-11 15:47:00 -0400
commit729f90e26802057f06905ab15a34612168eeac80 (patch)
tree41f8c4cedf10851b5b437aeeb558ce3d0f8db1dc /libavcodec/x86/h264_qpel_10bit.asm
parente1ce756844e684876318570dcebc74bc66c084f0 (diff)
downloadffmpeg-729f90e26802057f06905ab15a34612168eeac80.tar.gz
x86inc improvements for 64-bit
Add support for all x86-64 registers Prefer caller-saved register over callee-saved on WIN64 Support up to 15 function arguments Also (by Ronald S. Bultje) Fix up our asm to work with new x86inc.asm. Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com> Signed-off-by: Justin Ruggles <justin.ruggles@gmail.com>
Diffstat (limited to 'libavcodec/x86/h264_qpel_10bit.asm')
-rw-r--r--libavcodec/x86/h264_qpel_10bit.asm20
1 files changed, 11 insertions, 9 deletions
diff --git a/libavcodec/x86/h264_qpel_10bit.asm b/libavcodec/x86/h264_qpel_10bit.asm
index bdacf9f472..788d715d61 100644
--- a/libavcodec/x86/h264_qpel_10bit.asm
+++ b/libavcodec/x86/h264_qpel_10bit.asm
@@ -121,8 +121,8 @@ MCAxA_OP %1,%2,%3,%4,%5,%6,%7,%8
%endmacro
%macro MCAxA_OP 8
-cglobal %2_h264_qpel%5_%3_10_%1, %6,%7,%8
%if ARCH_X86_32
+cglobal %2_h264_qpel%5_%3_10_%1, %6,%7,%8
call stub_%2_h264_qpel%4_%3_10_%1
mov r0, r0m
mov r1, r1m
@@ -141,17 +141,19 @@ cglobal %2_h264_qpel%5_%3_10_%1, %6,%7,%8
call stub_%2_h264_qpel%4_%3_10_%1
RET
%else ; ARCH_X86_64
- mov r10, r0
- mov r11, r1
+cglobal %2_h264_qpel%5_%3_10_%1, %6,%7 + 2,%8
+ mov r%7, r0
+%assign p1 %7+1
+ mov r %+ p1, r1
call stub_%2_h264_qpel%4_%3_10_%1
- lea r0, [r10+%4*2]
- lea r1, [r11+%4*2]
+ lea r0, [r%7+%4*2]
+ lea r1, [r %+ p1+%4*2]
call stub_%2_h264_qpel%4_%3_10_%1
- lea r0, [r10+r2*%4]
- lea r1, [r11+r2*%4]
+ lea r0, [r%7+r2*%4]
+ lea r1, [r %+ p1+r2*%4]
call stub_%2_h264_qpel%4_%3_10_%1
- lea r0, [r10+r2*%4+%4*2]
- lea r1, [r11+r2*%4+%4*2]
+ lea r0, [r%7+r2*%4+%4*2]
+ lea r1, [r %+ p1+r2*%4+%4*2]
%if UNIX64 == 0 ; fall through to function
call stub_%2_h264_qpel%4_%3_10_%1
RET