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| author | Måns Rullgård <mans@mansr.com> | 2009-01-30 23:13:15 +0000 |
|---|---|---|
| committer | Måns Rullgård <mans@mansr.com> | 2009-01-30 23:13:15 +0000 |
| commit | dd927e2e62f499d3ed611042f91766bec20649ce (patch) | |
| tree | 94e05a6b239f1c1f8972ebe647501c5279ac70fd /libavcodec/arm | |
| parent | 8915009813620bce955e561f8f1726532c2fa446 (diff) | |
| download | ffmpeg-dd927e2e62f499d3ed611042f91766bec20649ce.tar.gz | |
ARM: NEON optimised vector_fmul
Originally committed as revision 16867 to svn://svn.ffmpeg.org/ffmpeg/trunk
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/dsputil_neon.c | 4 | ||||
| -rw-r--r-- | libavcodec/arm/dsputil_neon_s.S | 40 |
2 files changed, 44 insertions, 0 deletions
diff --git a/libavcodec/arm/dsputil_neon.c b/libavcodec/arm/dsputil_neon.c index d46fa61da8..2b1b2d32c3 100644 --- a/libavcodec/arm/dsputil_neon.c +++ b/libavcodec/arm/dsputil_neon.c @@ -146,6 +146,8 @@ void ff_h264_idct_add8_neon(uint8_t **dest, const int *block_offset, DCTELEM *block, int stride, const uint8_t nnzc[6*8]); +void ff_vector_fmul_neon(float *dst, const float *src, int len); + void ff_float_to_int16_neon(int16_t *, const float *, long); void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int); @@ -242,6 +244,8 @@ void ff_dsputil_init_neon(DSPContext *c, AVCodecContext *avctx) c->h264_idct_add16intra = ff_h264_idct_add16intra_neon; c->h264_idct_add8 = ff_h264_idct_add8_neon; + c->vector_fmul = ff_vector_fmul_neon; + if (!(avctx->flags & CODEC_FLAG_BITEXACT)) { c->float_to_int16 = ff_float_to_int16_neon; c->float_to_int16_interleave = ff_float_to_int16_interleave_neon; diff --git a/libavcodec/arm/dsputil_neon_s.S b/libavcodec/arm/dsputil_neon_s.S index 4f867149b9..9027353c4a 100644 --- a/libavcodec/arm/dsputil_neon_s.S +++ b/libavcodec/arm/dsputil_neon_s.S @@ -609,3 +609,43 @@ function ff_float_to_int16_interleave_neon, export=1 vcvt.s32.f32 q1, q1, #16 b 6b .endfunc + +function ff_vector_fmul_neon, export=1 + mov r3, r0 + subs r2, r2, #8 + vld1.64 {d0-d3}, [r0,:128]! + vld1.64 {d4-d7}, [r1,:128]! + vmul.f32 q8, q0, q2 + vmul.f32 q9, q1, q3 + beq 3f + bics ip, r2, #15 + beq 2f +1: subs ip, ip, #16 + vld1.64 {d0-d1}, [r0,:128]! + vld1.64 {d4-d5}, [r1,:128]! + vmul.f32 q10, q0, q2 + vld1.64 {d2-d3}, [r0,:128]! + vld1.64 {d6-d7}, [r1,:128]! + vmul.f32 q11, q1, q3 + vst1.64 {d16-d19},[r3,:128]! + vld1.64 {d0-d1}, [r0,:128]! + vld1.64 {d4-d5}, [r1,:128]! + vmul.f32 q8, q0, q2 + vld1.64 {d2-d3}, [r0,:128]! + vld1.64 {d6-d7}, [r1,:128]! + vmul.f32 q9, q1, q3 + vst1.64 {d20-d23},[r3,:128]! + bne 1b + ands r2, r2, #15 + beq 3f +2: vld1.64 {d0-d1}, [r0,:128]! + vld1.64 {d4-d5}, [r1,:128]! + vst1.64 {d16-d17},[r3,:128]! + vmul.f32 q8, q0, q2 + vld1.64 {d2-d3}, [r0,:128]! + vld1.64 {d6-d7}, [r1,:128]! + vst1.64 {d18-d19},[r3,:128]! + vmul.f32 q9, q1, q3 +3: vst1.64 {d16-d19},[r3,:128]! + bx lr + .endfunc |