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| author | Michael Niedermayer <michaelni@gmx.at> | 2013-01-20 13:57:10 +0100 |
|---|---|---|
| committer | Michael Niedermayer <michaelni@gmx.at> | 2013-01-20 13:57:10 +0100 |
| commit | cf061a9c3b861a048dd5b67ded5265c6f53805e5 (patch) | |
| tree | 7b939285a34abfe719f38e594afa105c41574014 /libavcodec/arm | |
| parent | b3b456b2588f67a152f3035cbc80d349898534c1 (diff) | |
| parent | aeaf268e52fc11c1f64914a319e0edddf1346d6a (diff) | |
| download | ffmpeg-cf061a9c3b861a048dd5b67ded5265c6f53805e5.tar.gz | |
Merge commit 'aeaf268e52fc11c1f64914a319e0edddf1346d6a'
* commit 'aeaf268e52fc11c1f64914a319e0edddf1346d6a':
vp3: integrate clear_blocks with idct of previous block.
mpegvideo: fix loop condition in draw_line()
dvdsubdec: parse the size from the extradata
Conflicts:
libavcodec/dvdsubdec.c
libavcodec/mpegvideo.c
Merged-by: Michael Niedermayer <michaelni@gmx.at>
Diffstat (limited to 'libavcodec/arm')
| -rw-r--r-- | libavcodec/arm/vp3dsp_neon.S | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/libavcodec/arm/vp3dsp_neon.S b/libavcodec/arm/vp3dsp_neon.S index 0c88562b45..f133905efe 100644 --- a/libavcodec/arm/vp3dsp_neon.S +++ b/libavcodec/arm/vp3dsp_neon.S @@ -108,14 +108,20 @@ endfunc function vp3_idct_start_neon vpush {d8-d15} + vmov.i16 q4, #0 + vmov.i16 q5, #0 movrel r3, vp3_idct_constants vld1.64 {d0-d1}, [r3,:128] - vld1.64 {d16-d19}, [r2,:128]! - vld1.64 {d20-d23}, [r2,:128]! - vld1.64 {d24-d27}, [r2,:128]! + vld1.64 {d16-d19}, [r2,:128] + vst1.64 {q4-q5}, [r2,:128]! + vld1.64 {d20-d23}, [r2,:128] + vst1.64 {q4-q5}, [r2,:128]! + vld1.64 {d24-d27}, [r2,:128] + vst1.64 {q4-q5}, [r2,:128]! vadd.s16 q1, q8, q12 vsub.s16 q8, q8, q12 - vld1.64 {d28-d31}, [r2,:128]! + vld1.64 {d28-d31}, [r2,:128] + vst1.64 {q4-q5}, [r2,:128]! vp3_idct_core_neon: vmull.s16 q2, d18, xC1S7 // (ip[1] * C1) << 16 @@ -345,10 +351,12 @@ function ff_vp3_idct_add_neon, export=1 endfunc function ff_vp3_idct_dc_add_neon, export=1 - ldrsh r2, [r2] + ldrsh r12, [r2] mov r3, r0 - add r2, r2, #15 - vdup.16 q15, r2 + add r12, r12, #15 + vdup.16 q15, r12 + mov r12, 0 + strh r12, [r2] vshr.s16 q15, q15, #5 vld1.8 {d0}, [r0,:64], r1 |